M5M44265CTP-6S MITSUBISHI, M5M44265CTP-6S Datasheet

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M5M44265CTP-6S

Manufacturer Part Number
M5M44265CTP-6S
Description
EDO (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic RAM
Manufacturer
MITSUBISHI
Datasheet

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Part Number:
M5M44265CTP-6S
Manufacturer:
MIT
Quantity:
416
1
DESCRIPTION
Microcomputer memory, Refresh memory for CRT, Frame Buffer
memory for CRT
This is a family of 262144-word by 16-bit dynamic RAMs with
Hyper Page mode fuction, fabricated with the high performance
CMOS process, and is ideal for the buffer memory systems of
personal computer graphics and HDD where high speed, low
power dissipation, and low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
512 cycles every 8.2ms.
FEATURES
PIN DESCRIPTION
XX=J,TP
APPLICATION
This device has 2CAS and 1W terminals with a refresh cycle of
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability*
Extended refresh capability
Hyper-page mode (512-column random access), Read-modify-
write, RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
*
M5M44265CXX-5,-5S
M5M44265CXX-6,-6S
M5M44265CXX-7,-7S
UCAS
DQ
RAS
LCAS
W
OE
V
The use of double-layer metalization process technology and a
A
V
Pin name
: Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S
CC
0
SS
Type name
CMOS Input level
CMOS Input level
M5M44265Cxx-5,-5S
M5M44265Cxx-6,-6S
M5M44265Cxx-7,-7S
Self refresh current
Extended refresh current
: option) only
~A
1
~DQ
8
16
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
Upper byte control
column address strobe input
(max.ns)
access
RAS
time
70
50
60
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Function
(max.ns)
access
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS
time
13
15
20
0
(max.ns)
0
Address
~A
access
~A
time
25
30
35
8
8
)
)*
(max.ns)
access
time
13
15
20
OE
(min.ns)
Cycle
130
110
550µW (Max)*
time
5.5mW (Max)
688mW (Max)
605mW (Max)
523mW (Max)
90
150µA (Max)
150µA (Max)
M5M44265CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
W
A
A
A
A
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
40
39
38
37
36
35
34
33
32
31
30
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
29
28
27
26
25
24
23
MITSUBISHI LSIs
29
31
30
NC: NO CONNECTION
V
V
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
SS
SS
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

Related parts for M5M44265CTP-6S

M5M44265CTP-6S Summary of contents

Page 1

... MITSUBISHI LSIs MITSUBISHI LSIs -5S,-6S,-7S V (5V ...

Page 2

... COLUMN DECODER SENSE REFRESH AMPLIFIER & CONTROL ROW & COLU- MN ADD- RESS MEMORY CELL ROW ~ A BUFF- 0 DECO (4194304 BITS) ER DER A 8 MITSUBISHI LSIs Input/Output DQ ~ OUT OPN D OUT D IN DNC D IN OPN D OUT OPN OPN OPN ...

Page 3

... Limits Typ Min 2 5.5V -10 OUT -10 , output open IH V -0. 0.2V or CAS V -0. -0. -0. -0. -0. ~1µs RAS min MITSUBISHI LSIs Unit ˚C ˚C Unit Max 0.4 V µ µA 125 110 1.0 * 0.1 125 110 mA 95 125 mA ...

Page 4

... Max Min Max Min OUT MITSUBISHI LSIs Unit Max Unit Max RAC ± ...

Page 5

... RCD RCD(max and RAD RAD(max) ASC and RCD RCD(max) ASC and V . IL(max) Parameter M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S (Note 22) (Note 22) MITSUBISHI LSIs Limits Min Max Min Max Min 8.2 8.2 128 128 ...

Page 6

... DQ pins WCS WCS(min and RWD RWD(min) AWD AWD(min) CPWD ) is indeterminate. IH MITSUBISHI LSIs Unit Max ns ns 10000 ns 10000 Unit Max ns ns 10000 10000 ns ns ...

Page 7

... CBR self refresh CAS hold time CHS 7 M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Parameter Min (Note 26) (Note 27) (Note 28) (Note 24) (Note 29) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Parameter Min M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Parameter Min 100 MITSUBISHI LSIs Limits Max Min Max Min 100000 ...

Page 8

... ASC CAH ROW COLUMN ADDRESS t RCS t DZC t CAC CLZ Hi-Z t RAC t DZO Indicates the don't care input. Note IH(min) Indicates the invalid output. MITSUBISHI LSIs RPC t CSH t RSH t CAS t RAL t CAL Hi-Z t REZ t OHR t OEA DATA VALID t OEA t OCH ...

Page 9

... IL 9 M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t RAD t RAH t t ASC CAH ROW COLUMN ADDRESS t RCS t DZC t CAC CLZ Hi-Z t RAC t DZO MITSUBISHI LSIs RPC t RSH t CAS t RAL t CAL t RRH Hi-Z Hi-Z t REZ t OHR DATA VALID t OEA t OCH t ORH RP t CRP t CPN t ASR ...

Page 10

... ~ (OUTPUTS M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t t RAH CAH t ASC ROW COLUMN ADDRESS t t WCS t DS DATA VALID RPC t RSH t CAS WCH t DH Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 11

... ~ ( (OUTPUTS M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t t RAH CAH t ASC COLUMN ROW ADDRESS t WCS t Hi DATA VALID Hi-Z MITSUBISHI LSIs RPC t RSH t CAS WCH CRP t ASR ROW ADDRESS ...

Page 12

... M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t RAH t ASC ROW COLUMN ADDRESS ADDRESS t RCS t DZC Hi-Z t CLZ Hi-Z t DZO MITSUBISHI LSIs RPC t RSH t CAS t CAH t CWL t RWL WCH DATA VALID Hi-Z t OEH t OEZ t ODD CRP t ...

Page 13

... V (OUTPUTS M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t RAH t ASC ROW COLUMN ADDRESS ADDRESS t RCS Hi-Z t DZC Hi-Z t CLZ Hi DZO MITSUBISHI LSIs RPC t RSH t CAS t CAH t CWL t RWL WCH DATA VALID Hi-Z t OEH OEZ t ODD CRP t ASR ...

Page 14

... RAH CAH t ASC COLUMN ROW ADDRESS ADDRESS t AWD t CWD t RCS t RWD t DZC Hi-Z t CAC CLZ Hi-Z VALID t RAC t t OEA DZO MITSUBISHI LSIs t RWC t RSH t CAS t CWL t RWL DATA VALID Hi-Z DATA t ODD t OEH t OEZ RPC t CRP t ASR ROW ...

Page 15

... RAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS t RWD Hi-Z t DZC Hi-Z t CAC CLZ Hi-Z DATA VALID t RAC t t DZO OEA MITSUBISHI LSIs t RWC RPC t RSH t CAS t CWL t RWL DATA VALID Hi-Z t ODD t OEH t OEZ t CRP t ASR ROW ADDRESS ...

Page 16

... ASC CAH CAH COLUMN-3 COLUMN-2 t RAL t t CAL CAL Hi CAC CAC DOH DOH DATA VALID CPA CPA MITSUBISHI LSIs ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 17

... ASC CAH CAH COLUMN-3 COLUMN-2 t RAL t t CAL CAL Hi-Z t CAC t AA DATA VALID-2 t CLZ t CPA Hi-Z t CAC DOH DATA VALID-1 t CPA MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t REZ t OHR t RDD t CDD t WEZ t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 18

... CSH RCD CAS ASC t RAH ASC CAH COLUMN WCS WCH WCS DATA VALID-1 MITSUBISHI LSIs RAS t t HPC RSH CAS CAS t t CAL CAL ASC CAH CAH COLUMN-3 COLUMN WCH WCS ...

Page 19

... WCS WCH DATA VALID-1 t RAS t t HPC RSH CAS CAS CAL CAL t t CAH CAH t ASC COLUMN-3 COLUMN WCH WCS WCH DATA VALID-3 Hi DATA VALID-2 Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 20

... ROW COLUMN-1 t AWD t t CWD RCS t RWD DZC Hi-Z t CAC CLZ Hi-Z DATA VALID-1 t RAC t ODD t t OEA DZO t OEZ MITSUBISHI LSIs t RAS t HPRWC t t CAS CAH CWL ASC COLUMN-2 t AWD t CWL t CWD t RCS CPWD DZC ...

Page 21

... ROW COLUMN-1 t AWD t t CWD RCS t RWD t t DZC DS Hi-Z t CAC CLZ Hi-Z DATA VALID-1 t RAC t ODD t t OEA DZO t OEZ MITSUBISHI LSIs t RAS t HPRWC t t CAS CAH CWL ASC COLUMN-2 t AWD t CWL t CWD t RCS CPWD Hi ...

Page 22

... COLUMN RCS WCS t CAL t DZC CAC WEZ t CLZ Hi-Z DATA VALID-1 t RAC t OEA t DZO t OEZ t OCH t ODD MITSUBISHI LSIs t RAS t t HPC HPRWC CAS CAS ASC t CAH CAH COLUMN-3 t CPWD t WCH t AWD t t CAL CWD DZC ...

Page 23

... ASC t CAH COLUMN CAL RCH t HCWD t HAWD t HPWD Hi-Z t CAC CPA WEZ DATA VALID-1 t HCOD t OEZ t HAOD t HPOD MITSUBISHI LSIs t CAS ASC CAH ASC COLUMN-2 t CAL t t WCS WCH DZC DS DATA VALID CPA t CLZ Hi-Z t DZC t ...

Page 24

... CAH CAH COLUMN-2 COLUMN-3 t RAL Hi CAC CAC DOH t CLZ Hi-Z DATA DATA VALID-1 VALID-2 t CPA t CPA t CHOL t OEZ t OEPE MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 25

... CAH COLUMN-2 COLUMN-3 t RAL t RCH t RCS t WPE Hi CAC CAC DOH t t CLZ WEZ Hi-Z DATA VALID CPA CPA MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 26

... V IH RAS CRP V IH LCAS/UCAS ASR ~ (INPUTS ~ (OUTPUTS M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t RAH ROW ADDRESS MITSUBISHI LSIs RPC Hi CRP t ASR ROW ADDRESS ...

Page 27

... ~ (INPUTS REZ t OHR t OFF t OHC ~ (OUTPUTS OEZ M5M44265CJ,TP-5,-6,-7,-5S,-6S,- RAS t RPC t CSR t CHR RAS CSR t RPC CHR Hi-Z MITSUBISHI LSIs t CRP t ASR ROW COLUMN ADDRESS ADDRESS t RCS ...

Page 28

... COLUMN ADDRESS t RCS t RAL t DZC t CAC CLZ Hi-Z t RAC t t DZO OEA t ORH Timing requirements and output state are the same as that of each cycle shown above. MITSUBISHI LSIs RAS t CHR t RRH Hi-Z DATA VALID ASR ROW ADDRESS t CDD t RDD t ...

Page 29

... RRH t RCH RDD t CDD V DQ ~ (INPUTS REZ t OHR t OFF t OHC ~ (OUTPUTS OEZ t ODD M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S t RASS t CSR MITSUBISHI LSIs t RPS t RPC t CRP t CHS t ASR ROW ADDRESS Hi-Z t RCS ...

Page 30

... Switching from self refresh operation to read/write operation. The time interval t the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. MITSUBISHI LSIs Read / Write Cycle t SND first refresh cycle ...

Page 31

... NSB SNB 8.2ms read/write cycles ~A ) are 0 8 2.2 RAS only burst refresh MITSUBISHI LSIs Read / Write t SNB refresh cycles last 511 cycles refresh cycles Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the ...

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