CY7C0852V-167AC Cypress Semiconductor Corporation., CY7C0852V-167AC Datasheet
CY7C0852V-167AC
Specifications of CY7C0852V-167AC
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CY7C0852V-167AC Summary of contents
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... CY7C0850V CY7C0851V 167 167 4.0 4.0 225 225 176TQFP 176TQFP 172FBGA 172FBGA • 3901 North First Street • San Jose CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 4-Mbit 9-Mbit (128K x 36) (256K x 36) CY7C0852V CY7C0853V 167 133 4.0 4.7 225 270 176TQFP 172FBGA 172FBGA , CA 95134 • 408-943-2600 Revised June 24, 2004 ...
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... Document #: 38-06070 Rev. *D I/O I/O Control Control True Dual-Ported RAM Array Address Address Decode Decode TMS Reset MRST TDI JTAG Logic TCK CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 9 DQ 27R 9 DQ 18R Addr. Read Back Mask Register CNT/MSK ...
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... VSS DQ25L DQ19L VSS VSS DQ19R TDI DQ7L DQ2L DQ2R DQ7R DQ5L DQ3L DQ0L DQ0R DQ3R DQ4L VDD DQ1L DQ1R VDD CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V DQ13R VSS CNTINTR DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R A0R INTR DQ27R DQ31R A1R NC DQ28R DQ34R ...
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... DQ26L DQ25L DQ19L VSS VSS DQ19R DQ18L TDI DQ7L DQ2L DQ2R DQ6L DQ5L DQ3L DQ0L DQ0R VSS DQ4L VDD DQ1L DQ1R CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V VDD DQ13R VSS NC DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R INTR DQ27R DQ31R A1R A17R DQ28R DQ34R ...
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... A 14L [ 15L [ 16L 43 DQ 24L 44 DQ 20L Document #: 38-06070 Rev. *D 176-pin Thin Quad Flat Pack (TQFP) Top View CY7C0850V CY7C0851V CY7C0852V CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 SS V ...
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... JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Power Inputs. CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Description . MAX is asserted LOW when L Page ...
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... Counter Hold X X Mask Reset L L Mask Load L H Mask Readback H X Reserved = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the 1 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V flag, a Write operation by R LOW. At least R Right Port R 0R–17R ...
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... Notes: 10. This section describes the CY7C0852V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850V has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF 11 ...
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... When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0850V/CY7C0851V/CY7C0852V as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This ...
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... Counter Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document #: 38-06070 Rev. *D Load/Increment 17 Mirror Increment Logic Wrap 17 Bit CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Mask Register Counter/ Address Address Decode Register Counter To Readback 1 and Address 0 Decode 17 Wrap Wrap Detect 17 To Counter ...
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... Value Reserved for version number. Defines Cypress part number for the CY7C0851V Defines Cypress part number for the CY7C0852V and CY7C0853V Defines Cypress part number for the CY7C0850V Allows unique identification of the DP family device vendor. Indicates the presence register. CY7C0850V/CY7C0851V ...
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... Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. ...
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... Description Test Conditions ° Input Capacitance MHz 3.3V Output Capacitance DD Input Capacitance Output Capacitance CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V + 0.5V DD Ambient Temperature V DD ° ° +70 C 3.3V ± 165 mV ° ° – +85 C 3.3V ± 165 mV -133 -100 2.4 2 ...
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... Vss < -167 CY7C0850V CY7C0850V CY7C0851V CY7C0851V CY7C0852V CY7C0852V Min. Max. Min. 167 6.0 7.5 2.7 3.0 2.7 3.0 2.0 2.0 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 2.3 2.5 0.6 0.6 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 3. 590 Ω 435 Ω 90% 10% < -133 -100 CY7C0853V CY7C0853V Max. Min. Max. Min. Max. 133 133 100 7.5 10.0 3.0 4.0 3.0 4.0 2.0 2.0 3.0 2.0 2.0 3.0 2.5 3.0 0.6 0.6 2.5 3.0 0.6 0 2.5 3.0 0.6 0.6 2.5 3.0 0.6 0 ...
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... Master Reset Set-up Time RSS t Master Reset Recovery Time RSR t Master Reset to Outputs Inactive RSF t Master Reset to Counter Interrupt RSCNTINT Flag Reset Time Document #: 38-06070 Rev. *D CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V -167 -133 CY7C0850V CY7C0850V CY7C0851V CY7C0851V CY7C0853V CY7C0852V CY7C0852V Min. Max. Min. Max. Min. 4.0 4 4.0 0 4.4 0 4.0 4.4 4.0 4.4 4.0 4.4 1.0 1 ...
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... Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06070 Rev. *D Description TMSS t TMSH t TDIS t TDIH t TDOX CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 167/133/100 Min. Max. 10 100 TCYC t TDOV Page Unit MHz ...
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... Document #: 38-06070 Rev RSR ACTIVE t CYC2 t CL2 A A n+1 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V IL CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V n+2 n n+1 t OHZ t OLZ t OE constantly loads the address on the rising edge of the CLK n+2 Page ...
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... SA HA DATA IN DATA OUT Notes: 26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data sheet. ADDRESS = ADDRESS . (B1) (B2) 27. ADS = CNTEN= B0 – LOW; MRST = CNTRST = CNT/MSK = HIGH. 28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. ...
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... Document #: 38-06070 Rev. *D [25, 28, 30, 31 n+1 n n+2 t CD2 OHZ READ WRITE [30] t SAD t SCN t CD2 READ WITH COUNTER CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V n+3 n+4 D n+3 READ t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER n+5 t CD2 Q n+4 Q n+3 Page ...
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... ADDRESS n INTERNAL A ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D DATA WRITE EXTERNAL ADDRESS Document #: 38-06070 Rev. *D [31 n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V A A n+2 n n+2 n+3 WRITE WITH COUNTER A n+4 n+4 Page ...
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... No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06070 Rev CD2 t CKLZ WRITE READ ADDRESS 0 ADDRESS 1 ADDRESS 0 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V CD2 READ ...
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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06070 Rev. *D [34, 35, 36, 37 CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V n+4 n+2 n n+1 n+2 n+3 Page ...
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... HD CKLZ CCS CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V t CD2 violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...
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... CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 44. The mask register assumed to have the value of 1FFFFh. 45. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06070 Rev. *D [41, 42, 43, 44, 45] 1FFFE 1FFFD 1FFFF t SCINT CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V Last_Loaded Last_Loaded +1 t RCINT Page ...
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... SINT 3FFFF m+1 m [1, 8, 51, 52 CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V A A n+2 n+3 t RINT A m+3 Outputs – DQ Operation 0 35 High-Z Deselected High-Z Deselected D Write IN D Read OUT High-Z Outputs Disabled A m+4 Page ...
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... Ordering Code 133 CY7C0853V-133BBC CY7C0853V-133BBI 100 CY7C0853V-100BBC CY7C0853V-100BBI 128K × 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM Speed (MHz) Ordering Code 167 CY7C0852V-167BBC CY7C0852V-167AC 133 CY7C0852V-133BBC CY7C0852V-133BBI CY7C0852V-133AC CY7C0852V-133AI 64K × 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM Speed (MHz) Ordering Code 167 CY7C0851V-167BBC CY7C0851V-167AC ...
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... Package Diagrams 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 Document #: 38-06070 Rev. *D CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 51-85132-** Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 172-Ball FBGA ( 1.25 mm) BB172 CY7C0850V/CY7C0851V CY7C0852V/CY7C0853V 51-85114-*B Page ...
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... Document History Page Document Title: CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V FLEx36 nous Dual-Port RAM Document Number: 38-06070 Issue REV. ECN NO. Date ** 127809 08/04/03 *A 210948 See ECN *B 216190 See ECN *C 231996 See ECN *D 238938 See ECN Document #: 38-06070 Rev. *D Orig. of Change Description of Change SPN This data sheet has been extracted from another data sheet: the 2M/4M/9M data sheet ...