CY7C146-55JI Cypress Semiconductor Corporation., CY7C146-55JI Datasheet

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CY7C146-55JI

Manufacturer Part Number
CY7C146-55JI
Description
CY7C146-55JI2Kx8 Dual-Port Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Notes:
Cypress Semiconductor Corporation
• True Dual-Ported memory cells which allow simulta-
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
• BUSY output flag on CY7C132/CY7C136; BUSY input
• INT flag for port-to-port communication (52-pin
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
• Pin-compatible and functionally equivalent to
1.
2.
neous reads of the same memory location
width to 16 or more bits using slave CY7C142/CY7C146
on CY7C142/CY7C146
PLCC/PQFP versions)
52-pin TQFP (CY7C136/146)
IDT7132/IDT7142
Logic Block Diagram
BUSY
CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
Open drain outputs; pull-up resistor required.
INT
R/W
I/O
I/O
A
OE
CE
A
L
L
10L
7L
0L
[1]
0L
[2]
L
L
L
DECODER
ADDRESS
R/W
CC
CE
OE
L
L
L
CONTROL
= 90 mA (max.)
I/O
(7C132/7C136 ONLY)
(7C136/7C146 ONLY)
INTERRUPTLOGIC
ARBITRA TION
MEMORY
ARRAY
LOGIC
AND
3901 North First Street
CONTROL
I/O
DECODER
ADDRESS
CE
OE
R/W
R
R
R
Functional Description
The
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER du-
al-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. On the PLCC version, INT
is an interrupt flag indicating that data has been placed in a
unique location (7FF for the left port and 7FE for the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
CY7C132/CY7C136/CY7C142
2Kx8 Dual-Port Static RAM
San Jose
A
INT
R/W
CE
OE
I/O
I/O
BUSY
A
10R
0R
7R
0R
R
R
R
December 1989 – Revised March 27, 1997
R
[2]
C132-1
R
[1]
CY7C132/CY7C136
CY7C142/CY7C146
CA 95134
Pin Configuration
BUSY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R/W
A
GND
CE
OE
10L
A
A
A
A
A
A
A
A
A
A
0L
1L
2L
3L
4L
5L
6L
7L
0L
1L
2L
3L
4L
5L
6L
7L
8L
9L
L
L
L
L
and
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
7C132
7C142
DIP
fax id: 5201
CY7C146
408-943-2600
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CE
R/W
A
OE
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BUSY
CC
C132-2
10R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
6R
5R
4R
3R
2R
1R
0R
R
R
R
R
are

Related parts for CY7C146-55JI

CY7C146-55JI Summary of contents

Page 1

... CC • Fully asynchronous operation • Automatic power-down • Master CY7C132/CY7C136 easily expands data bus width more bits using slave CY7C142/CY7C146 • BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146 • INT flag for port-to-port communication (52-pin PLCC/PQFP versions) • ...

Page 2

... C to +150 C Latch-Up Current .................................................... >200 mA Operating Range +125 C Range 0.5V to +7.0V Commercial 0.5V to +7.0V Industrial 3.5V to +7.0V [5] Military Note the “instant on” case temperature CY7C132/CY7C136 CY7C142/CY7C146 PQFP Top View 7C136 33 7C146 ...

Page 3

... Mil > V – 0. < 0.2V, [9] MAX Test Conditions MHz 5.0V CC and using AC Test Waveforms input levels of GND to 3V CY7C132/CY7C136 CY7C142/CY7C146 [3] 7C132-30 7C132-35 7C132-45,55 7C136-25,30 7C136-35 7C136-45,55 7C142-30 7C142-35 7C142-45,55 7C146-25,30 7C146-35 7C146-45,55 Min. Max. Min. Max. Min. Max. ...

Page 4

... CY7C132/CY7C136 CY7C142/CY7C146 5V 281 BUSY OR INT 30pF C132-6 C132-5 BUSYOutput Load (CY7C132/CY7C136 ONLY) ALL INPUT PULSES 90% 90% 10% < [3] 7C132-25 7C132-30 7C136-25 7C136-30 7C142-25 7C142-30 7C146-25 7C146-30 Min. Max. ...

Page 5

... Min. Max. 35 [12 [12] 35 [12 [10] 0 [10 CY7C132/CY7C136 CY7C142/CY7C146 [3] 7C132-25 7C132-30 7C136-25 7C136-30 7C142-25 7C142-30 7C146-25 7C146-30 Min. Max. Min. Max Note ...

Page 6

... These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. CY7C142/CY7C146 only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’ ...

Page 7

... IL 22. Address valid prior to or coincident with CE transition LOW. [20, 21 [20, 22] t ACE t DOE DATA VALID t RC ADDRESS MATCH t PWE PS ADDRESS MATCH t BLA CY7C132/CY7C136 CY7C142/CY7C146 DATA VALID t HZCE t HZOE t PD VALID t BHA t BDD t DDD WDD C132-7 C132-8 VALID C132-9 ...

Page 8

... PWE t SD DATA VALID HIGH IMPEDANCE [15, 24 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE allow the data I/O pins to enter high impedance and for data PWE HZWE SD 8 CY7C132/CY7C136 CY7C142/CY7C146 C132- LZWE C132-11 ...

Page 9

... BUSY R Right Address Valid First: ADDRESS ADDRESS MATCH ADDRESS L BUSY L ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 9 CY7C132/CY7C136 CY7C142/CY7C146 t BHC C132-12 t BHC C132-13 C132-14 C132-15 ...

Page 10

... Switching Waveforms (continued) Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146 BUSY [19] Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS R INT R Right Side Clears INT : R ADDRESS R INT R t PWE t WC WRITE 7FF t INS ...

Page 11

... Interrupt Timing Diagrams Right Side Sets INT : L ADDRESS R INT L Right Side Clears INT : L ADDRESS R INT L (continued WRITE 7FE t INS HA t EINS t WINS EINR 11 CY7C132/CY7C136 CY7C142/CY7C146 C132- READ 7FE t INR t OINR C132-20 ...

Page 12

... AMBIENTTEMPERATURE(°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4.5V CC 5.0 T =25° 200 400 600 800 1000 CAPACITANCE(pF) 12 CY7C132/CY7C136 CY7C142/CY7C146 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 =5. =25° 1.0 2.0 3.0 4.0 OUTPUTVOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 ...

Page 13

... L69 52-Square Leadless Chip Carrier J69 52-Lead Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack J69 52-Lead Plastic Leaded Chip Carrier L69 52-Square Leadless Chip Carrier 13 CY7C132/CY7C136 CY7C142/CY7C146 Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial ...

Page 14

... CY7C146-35JC CY7C146-35NC CY7C146-35JI CY7C146-35LMB 45 CY7C146-45JC CY7C146-45NC CY7C146-45JI CY7C146-45LMB 55 CY7C146-55JC CY7C146-55NC CY7C146-55JI CY7C146-55LMB Shaded area contains preliminary information. Package Name Package Type P25 48-Lead (600-Mil) Molded DIP P25 48-Lead (600-Mil) Molded DIP P25 48-Lead (600-Mil) Molded DIP P25 48-Lead (600-Mil) Molded DIP ...

Page 15

... WINS 10, 11 EINS 10, 11 INS 10, 11 OINR 10, 11 EINR 10, 11 INR BUSY TIMING [ 10, 11 BDD Note: 25. CY7C142/CY7C146 only. Document #: 38-00061-K 15 ...

Page 16

... Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 52-Lead Plastic Leaded Chip Carrier J69 16 CY7C132/CY7C136 CY7C142/CY7C146 ...

Page 17

... Package Diagrams (continued) 52-Square Leadless Chip Carrier L69 52-Lead Plastic Quad Flatpack N52 17 CY7C132/CY7C136 CY7C142/CY7C146 ...

Page 18

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead (600-Mil) Molded DIP P25 CY7C132/CY7C136 CY7C142/CY7C146 ...

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