CY7C4281-25JC Cypress Semiconductor Corporation., CY7C4281-25JC Datasheet
CY7C4281-25JC
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CY7C4281-25JC Summary of contents
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Features • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — I =50 mA ...
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Pin Configurations PLCC Top View ...
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Pin Definitions Signal Name Description D Data Inputs 0–17 Q Data Outputs 0–17 WEN Write Enable REN Read Enable WCLK Write Clock RCLK Read Clock WXO/HF Write Expansion Out/Half Full Flag EF Empty Flag FF Full Flag PAE Programmable Almost ...
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Maximum Ratings [1] (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................– +150 C Ambient Temperature with Power Applied............................................– +125 C Supply Voltage to Ground Potential ............... –0.5V ...
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AC Test Loads and Waveforms R1 1.1K 5V OUTPUT 680 INCLUDING 4275–4 JIG AND SCOPE Switching Characteristics Over the Operating Range Parameter t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK ...
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Switching Characteristics Over the Operating Range (continued) Parameter t Clock to Programmable Almost-Full Flag PAEsynch (Synchronous mode Clock to Half-Full Flag HF t Clock to Expansion Out XO t Expansion in Pulse Width XI t Expansion in Set-Up ...
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Switching Waveforms Write Cycle Timing WCLK D – WEN FF t SKEW1 RCLK REN Read Cycle Timing RCLK t ENS REN EF Q – OLZ OE WCLK WEN Notes: 14 the minimum time ...
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Switching Waveforms (continued) [16] Reset Timing RS REN, WEN, LD EF,PAE FF,PAF – 17 First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ...
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Switching Waveforms (continued) Empty Flag Timing WCLK – ENH ENS WEN t FRL RCLK t SKEW2 EF REN OE Q – Full FlagTiming NO WRITE WCLK [14] t SKEW1 D ...
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Switching Waveforms (continued) Half-Full Flag Timing WCLK WEN HF HALF FULL OR LESS RCLK REN Programmable Almost Empty Flag Timing WCLK WEN [20] PAE RCLK REN Note: 20. PAE is offset = n. Number of data words into FIFO already ...
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Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) t CLKH WCLK WEN PAE t SKEW3 RCLK REN Programmable Almost Full Flag Timing WCLK WEN [25] PAF RCLK REN Notes: 21. PAE offset n. ...
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Switching Waveforms (continued) Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW)) t CLKH WCLK WEN PAF FULL– WORDS RCLK REN Write Programmable Registers t CLK t CLKH WCLK t ENS LD t ENS ...
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Switching Waveforms (continued) Read Programmable Registers t CLK t CLKH RCLK t ENS LD t ENS WEN Q – Write Expansion Out Timing WCLK WXO t ENS WEN Read Expansion Out Timing WCLK RXO t ENS REN Write ...
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Switching Waveforms (continued) Read Expansion In Timing RXI RCLK [33, 34, 35] Retransmit Timing FL/RT REN/WEN EF/FF and all async flags HF/PAE/PAF Notes: 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as ...
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Architecture The CY7C4275/85 consists of an array of 32K/64K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, ...
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Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. ...
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Width Expansion Configuration The CY7C4275/85 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- pansion mode all control line inputs are common and all flags are available. Empty (Full) flags ...
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Depth Expansion Configuration (with Programmable Flags) The CY7C4275/85 can easily be adapted to applications re- quiring more than 32,768/65,536 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these ...
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Ordering Information 32Kx18 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4275–10ASC CY7C4275–10ASI 15 CY7C4275–15ASC 25 CY7C4275–25ASC 64Kx18 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4285–10ASC CY7C4285–10ASI 15 CY7C4285–15ASC 25 CY7C4285–25ASC Document #: 38-06008 Rev. *A Package Package Name ...
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Package Diagrams Document #: 38-06008 Rev. *A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a ...
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Document Title: CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number: 38-06008 Issue REV. ECN NO. Date ** 106469 07/12/01 *A 122260 12/26/02 Document #: 38-06008 Rev. *A Orig. of Change SZV Change from Spec Number: 38-00588 to 38-06008 ...