CY7C372 Cypress Semiconductor Corporation., CY7C372 Datasheet

CY7C372

Manufacturer Part Number

CY7C372

Description

UltraLogic?64-Macrocell Flash CPLD

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C372.pdf (1 pages)

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Features

Functional Description

The CY7C372 is a Flash erasable Complex Programmable

Logic Device (CPLD) and is part of the F

high-density, high-speed CPLDs. Like all members of the

Selection Guide

Cypress Semiconductor Corporation

Maximum Propagation Delay, t

Minimum Set-up, t

Maximum Clock to Output, t

Maximum Supply

Current, I

Shaded areas contain preliminary information.

• 64 macrocells in four logic blocks

• 32 I/O pins

• 6 dedicated inputs including 2 clock pins

• Bus Hold capabilities on all I/Os and dedicated inputs

• No hidden delays

• High speed

• Electrically alterable Flash technology

• Available in 44-pin PLCC and CLCC packages

• Pin compatible with the CY7C371

LASH

— f

— t

I/O

370 family, the CY7C372 is designed to bring the ease

MAX

I/O

= 5.5 ns

I/O

= 10 ns

= 6.5 ns

= 125 MHz

(mA)

8 I/Os

(ns)

BLOCK

LOGIC

(ns)

Commercial

Military/Industrial

MACROCELLS

LASH

•

3901 North First Street

370 family of

INPUT

UltraLogic™ 64-Macrocell Flash CPLD

For new designs see CY7C372i

INPUTS

PIM

7C372-125

INPUTS

CLOCK

280

5.5

6.5

of use and high performance of the 22V10 to high-density

CPLDs.

The 64 macrocells in the CY7C372 are divided between four

logic blocks. Each logic block includes 16 macrocells, a

72 x 86 product term array, and an intelligent product term

allocator.

The logic blocks in the F

with an extremely fast and predictable routing resource—the

Programmable Interconnect Matrix (PIM). The PIM brings flex-

ibility, routability, speed, and a uniform delay to the intercon-

nect.

Like all members of the F

in I/O resources. Every two macrocells in the device feature an

associated I/O pin, resulting in 32 I/O pins on the CY7C372. In

addition, there are four dedicated inputs and two input/clock

pins.

Finally, the CY7C372 features a very simple timing model. Un-

like other high-density CPLD architectures, there are no hid-

den speed delays such as fanout effects, interconnect delays,

or expander delays. Regardless of the number of resources

used or the type of application, the timing parameters on the

CY7C372 remain the same.

INPUT/CLOCK

MACROCELLS

•

7C372-100

San Jose

250

6.5

BLOCK

LOGIC

December 1992 – Revised April 20, 1998

7C372-83

•

LASH

250

300

LASH

CA 95134

370 architecture are connected

370 family, the CY7C372 is rich

8 I/Os

7C372-66

7c372–1

250

300

•

I/O

CY7C372

fax id: 6127

408-943-2600

I/O

7C372L-66

125

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