MT9074AP Mitel, MT9074AP Datasheet
MT9074AP
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MT9074AP Summary of contents
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... DSTo ST-BUS CSTo Interface RxDLCLK RxDL T1/E1/J1 Single Chip Transceiver DS5024 MT9074AP MT9074AL Description The MT9074 is a single chip device, operable in either mode, integrating either an advanced T1 (T1 mode) or PCM 30 (E1 mode) framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane ...
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MT9074 CS RESET IRQ VSS IC INT/MOT VDD R/W/WR AC0 RESET IRQ VSS IC 92 INT/MOT VDD 94 ...
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Advance Information Pin Description Pin # Name 68 Pin 100 Pin PLCC MQFP 1 66 OSC1 Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2 where a crystal is used directly driven when ...
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MT9074 Pin Description Pin # Name 68 Pin 100 Pin PLCC MQFP 17 90 Vss Negative Power Supply (Input). Digital ground Internal Connection. Tie to Vss (ground) for normal operation INT/MOT Intel/Motorola Mode Selection (Input).A ...
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Advance Information Pin Description Pin # Name 68 Pin 100 Pin PLCC MQFP 42 23 RxMF Receive Multiframe Boundary (Output). An output pulse delimiting the received multiframe boundary. The next frame output on the data stream (DSTo) is basic frame ...
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MT9074 Pin Description Pin # Name 68 Pin 100 Pin PLCC MQFP 61 57 LOS Loss of signal or synchronization (Output).When high, and LOS/LOF (page 02H address 13H bit 2) is zero, this signal indicates that the receive portion of ...
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Advance Information To accommodate some special applications, the MT9074 also supports a digital framer only mode by providing direct access to the transmit and receive data in digital format, i.e. by-passing the analog LIU front-end. The digital portion of the ...
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MT9074 attenuated 1024 kHz (translates to 2000 m. of PIC 0.65mm or 22 AWG cable) and tolerate jitter to the maximum specified by ETS 300 011 (Figure 4). The LOS output pin function is ...
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Advance Information Peak to Peak Jitter Amplitude (log scale) 18UI 1.5UI 0.2UI 1.667Hz Figure 4 - Input Jitter Tolerance as recommended by ETSI 300 011 (E1) Name TXL2-0 Transmit Line Build Out Setting these bits shapes the ...
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MT9074 Name TX2-0 Transmit pulse amplitude. Select the TX2 –TX0 bits according to the line type, value of termination resistors (RT), and transformer turns ratio used TX2 TX1 TX0 ...
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Advance Information 1.20 1.05 0.95 0.90 0.80 0.50 0.05 0 -0.05 -0.26 -0.45 Time (Nanoseconds) Time U.I. Normalized Amplitude Time (Nanoseconds) Time U.I. Normalized Amplitude Note: One Unit Interval = 648 nanoseconds Time, in unit intervals (UI) Figure 7 - ...
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MT9074 Percentage of Nominal Peak Voltage 120 110 100 -10 -20 20 Mhz Clock The MT9074 requires a 20 Mhz clock. This may provided ppm oscillator as per Figure 9. 20MHz OSC1 ...
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Advance Information dB -0.5 0 19.5 10 Figure 11- TR 62411 Jitter Attenuation Curve Phase Lock Loop (PLL) The MT9074 contains a PLL, which can be locked to either an input 4.096 Mhz clock or the extracted line clock.The PLL ...
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... This results in a single time slot data rate of 8 bits x 8000/sec kbits/sec. It should be noted that the Mitel ST-BUS has 32 channels numbered 0 to 31. When mapping to the DS1 payload only the first 24 time slots and the last (time slot 31, for the overhead bit ST-BUS are used (see Table 6) ...
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Advance Information The SLC-96 frame structure is similar to the D4 frame structure, except a facility management overlay is superimposed over the erstwhile Fs bits, see Table 9. The protocol appropriate for the application is selected via the Framing Mode ...
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... This results in a single time slot data rate of 8 bits x 8000/sec kbits/sec. It should be noted that the Mitel ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7 (see Mitel Application Note MSAN-126). Therefore, ST- BUS bit 7 is synonymous with PCM 30 bit 1 ...
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Advance Information Basic Frame Alignment Time slot 0 of every basic frame is reserved for basic frame alignment and contains either a Frame Alignment Signal (FAS Non-Frame Alignment Signal (NFAS). FAS and NFAS occur in time slot zero ...
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MT9074 position one of the four FASs of the following submultiframe before it is transmitted (see Table 12). The submultiframe is then transmitted and, at the far end, the same process occurs. That is, a CRC-4 remainder is generated for ...
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Advance Information G.704 and G.732 for more details on CAS multiframing requirements. A CAS signalling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition rate of 2 msec. It should be noted that ...
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MT9074 successive read/write operations to the HDLC FIFO is required. Table 13 associates the MT9074 control and status pages with access and page descriptions. Identification Code The MT9074 shall be identified by the code 10101111, read from the identification code ...
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Advance Information Data Link Operation Data Link Operation in E1 mode In E1 mode MT9074 has a user defined kbit/s data link for transport of maintenance and performance monitoring information across the PCM 30 ...
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MT9074 Octet # ...
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Advance Information messages, a new message must be present the last 10 appropriate byte positions before being loaded into the receive BIOM register. When a new message has been received, a maskable interrupt (maskable by setting bit ...
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MT9074 N bytes of data. The HDLC does not distinguish between the control and information fields and a packet does not need to contain an information field to be valid. The FCS field, which precedes the closing flag, consists of ...
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Advance Information well as a receive to transmit loopback are also supported. Transmit and receive bit rates and enables can operate independently. In MT9074 the transceiver can operate at a continuous rate independent of RXcen and TXcen (free run mode) ...
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MT9074 flag followed by the data and closing flag is sent and zero insertion still included, but no CRC. That is, the FCS is injected by the microprocessor as part of the data field. This is used in V.120 terminal ...
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Advance Information updated by each end of packet (closing flag) received and therefore should be read when an end of packet is received so that the next packet does not overwrite the registers. Slip Buffers Slip Buffer in T1 mode ...
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MT9074 (TSLPD). The relative phase delay between the system frame boundary and the transmit elastic frame read boundary is measured every frame and reported in the Transmit Slip Buffer Delay register- (page 3H, address 17H). In addition the relative offset ...
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Advance Information system the receive data is in phase with the E1.5o clock, the C4b clock is phase-locked to the E1.5o clock, and the read and write positions of the slip buffer will remain fixed with respect to each other. ...
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MT9074 channels from the write pointer, a slip will occur, which will put the read pointer 28 channels from the write pointer. This provides a worst case hysteresis of 13 channels peak (26 channels peak-to-peak wander tolerance of ...
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Advance Information After power-up, the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM 30 receive bit stream. Once the FAS is detected, the corresponding bit 2 of the non-frame alignment signal (NFAS) is ...
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MT9074 >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe ...
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Advance Information Fs bits are checked (FSI set high). If the D4 secondary yellow alarm is enabled (control bit 1 - D4SECY of Transmit Alarm Control Word page 1H, address 11H) then the Fs bit of frame 12 is not ...
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MT9074 will become unfrozen synchronization is acquired. When the CAS signalling interrupt is unmasked (page 01H, address 1EH, SIGI=0), pin IRQ (pin 12 in PLCC MQFP) will become active when a signalling nibble state change is detected in ...
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Advance Information Associated with each counter is a maskable event occurrence interrupt and a maskable counter overflow interrupt. Overflow interrupts are useful when cumulative error counts are being recorded. For example, every time the framing bit error counter overflow interrupt ...
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MT9074 Bipolar Violation Error Counter (BPV15-BPV0) The bipolar violation error counter will count bipolar violations or encoding errors that are not part of B8ZS encoding. This counter BPV15-BPV0 is 16 bits long (page 4H, addresses 16H and 17H) and is ...
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Advance Information PRBS counter overflow (PRBSO) interrupt (page 1, address 1DH) is associated with this counter. CRC Multiframe Counter for PRBS (PSM7-0) This eight bit counter counts receive CRC-4 multiframes. It can be directly loaded via the microport. The counter ...
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MT9074 Digital Milliwatt If the control bit ADSEQ is one, a digital milliwatt sequence (Table 18 mode or (Table 19 mode may be transmit on any combination of selected channels. The channels are selected by setting ...
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Advance Information more than a millisecond or when more than 192 zeros have been received in a row. A loss of signal condition will terminate when an average ones density of at least 12.5% has been received over a period ...
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MT9074 interrupt registers are cleared IRQ will return to a high impedance state. This function can also be accomplished by toggling the INTA bit (page 1, address 1AH). All the interrupts of the MT9074 in T1 and E1 mode are ...
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Advance Information Digital Framer Mode T1 mode Setting bit 4 in the Configuration Control Word (address 10H of Master Control Page 2) disables the LIU and converts the MT9074 into a digital T1 transceiver. The digital 2.048 backplane maps into ...
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MT9074 Control and Status Registers T1 Mode Master Control 1 (Page 01H) (T1) Address ( 10H (Table 21) Framing Mode Select 11H (Table 22) Transmit Alarm Control Word 12H (Table ...
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Advance Information Bit Name Functional Description 7 ESF Extended Setting this transmission and reception of the 24 frame superframe DS1 protocol. 6 SLC96 SLC96 Mode Select. Setting this bit enables input and output of the Fs bit pattern on the ...
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MT9074 Bit Name Functional Description 7 ESFYEL ESFYellow Alarm. Setting this bit while in ESF mode causes a repeating pattern of eight 1’s followed by eight 0’ insert onto the transmit FDL (JTS bit set low - see ...
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Advance Information Bit Name Functional Description 1 JTS Japan Telecom nization. Setting this bit forces the inclusion of Sbits in the CRC-6 calculation. 0 H1R64 HDLC1 Rate Select. Setting this pin high while HDLC1 is activated enables 64 Kb/s operation ...
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MT9074 Bit Name Functional Description 7 RxB8ZS Receive B8ZS Enable. If one, receive B8ZS enabled. 6 MLBK Metallic Loopback. If one, then RRTIP/RRING directly to respectively. If zero, this feature is disabled. Set the transmit line build out to -7.5dB ...
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Advance Information Bit Name Functional Description 7-0 TxM7-0 Transmit Message Bits The contents of transmitted into those outgoing DS1 channels selected by the Per Time Slot Control registers. Table 29 - Transmit Message Word (T1) (Page 1, ...
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MT9074 Bit Name Functional Description 2 EXTOSC External Oscillator Setting this bit connects the pin OSC1 to a TTL compatible input. This allows for a system design employing a TTL output oscillator as a 20.000 Mhz reference clock. 1 RSV ...
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Advance Information Bit Name Functional Description 3 BPVIM Bipolar Violation Mask. When interrupt is initiated whenever a bipolar violation B8ZS encoding) is encountered unmasked masked. 2 PRBSIM Psuedo Sequence Mask. When interrupt will be generated upon ...
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MT9074 Bit Name Functional Description 7 Unused. 4 LCDIM Loop Code Detected Interrupt Mask. When interrupt is triggered when either the loop up (00001) or loop down (001) code has been detected on the line for a ...
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Advance Information Master Control 2 (Page 02H) (T1) Address ( 10H (Table 38) Configuration Control Word 11H (Table 39) Custom Tx Pulse Enable 12H Reserved 13H Reserved 14H Reserved 15H ...
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MT9074 Bit Name Functional Description 7 T1/E1 T1/E1 mode selection. when this bit is zero, the device mode. When set high, the device mode. 6-5 RSV Reserved. Must be kept at 0 for normal ...
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Advance Information Bit Name Functional Description 7 RSV Reserved. Must be kept at 0 for normal operation. 6-0 CP6-0 Custom Pulse. These bits provide the capability for magnitude setting for the TTIP/TRING line driver A/D converter during the second phase ...
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MT9074 Master Status 1 (Page03H) (T1) Address ( 10H (Table 45) Synchronization Status Word 11H (Table 46) Alarm Status Word 12H (Table 47) Timer Status Word 13H (Table 48) Most ...
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Advance Information Bit Name Functional Description 7 TFSYNC Terminal Frame Synchroniza- tion. Indicates the Terminal Frame Synchronization status (1 - loss acquired). For ESF links terminal frame synchroni- zation and multiframe synchro- nization are synonymous. 6 MFSYN Multiframe ...
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MT9074 Bit Name Functional Description 7 1SEC One Second Timer Status. This bit changes state once every 0.5 seconds. 6 2SEC Two Second Timer Status. This bit changes state once every second and is synchronous with the 1SEC timer. 5 ...
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Advance Information Bit Name Functional Description PD4 - Peak Detector PD0 These five bits indicate the level of the received signal AMI pulses. PD4 PD3 PD2 PD1 PD0 ...
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MT9074 Master Status 2 (Page04H)(T1) Address ( 10H (Table 56) PRBS Error Counter 11H (Table 57) CRC Multiframe counter for PRBS 12H (Table 58) Alarm Reporting Latch 13H (Table 59) ...
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Advance Information Bit Name Functional Description PS7-0 This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 56 - PRBS Error Counter (Page 4, Address ...
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MT9074 Bit Name Functional Description OOF3 - 0 Out Of Frame Counter. This four bit counter is incremented with every loss synchronization COFA3 - 0 Change of Frame Alignment Counter. This four bit counter ...
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Advance Information Bit Name Functional Description 7 TFSYNI Terminal Frame Synchronization Interrupt. When unmasked this interrupt bit goes high whenever a change of state of terminal frame synchronization Reading this register clears this bit. 6 MFSYNI Multiframe Interrupt. When unmasked ...
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MT9074 Bit Name Functional Description 7 FEO Framing Bit Error Counter Overflow unmasked this interrupt bit goes high framing changes from FFH to 00H. Reading this register clears this bit. 6 CRCO CRC-6 Overflow unmasked this interrupt bit goes high ...
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Advance Information Bit Name Functional Description Unused. 6 HDLC0I HDLC0 Interrupt. Whenever an unmasked HDLC0 interrupt occurs (from the 4 kHz data link) this bit goes high. Reading this register clears this bit. 5 HDLC1I HDLC1 ...
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MT9074 Bit Name Functional Description 7 FEOL Framing Counter Overflow Latch. This bit is set when the framing overflows cleared after being read. 6 CRCOL CRC-6 Overflow Latch. This bit is set when the crc error counter overflows. ...
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Advance Information Per Channel Transmit Signalling (Pages 5 and 6) (T1) Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit Signalling Control Words for DS1 channels and ...
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MT9074 Bit Name A(n), Transmit Signalling Bits for Channel n. When control bit MSN = 1 and RPSIG = 1 this nibble is used. For ESF links these 4 bits are transmitted on the associated B(n) DS1 ...
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Advance Information Bit Name Functional Description 7 TXMSG Transmit Message Mode. If high, the data contained in the Transmit Message Register (address 18H, page 1) is transmitted in the corresponding DS1 time slot. If zero, the data transmitted on the ...
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MT9074 Per Channel Receive Signalling (T1 and E1 mode) (Pages 9 and 0AH) Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive Signalling Control Words for DS1 channels and 17 ...
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Advance Information E1 Mode Master Control 1 (Page 01H) (E1) Address ( 10H (Table 79) Mode Selection Control Word 11H (Table 80) Transmit Alarm Control Word 12H (Table 81) HDLC ...
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MT9074 Bit Name Functional Description 7 ASEL AIS Select. This bit selects the criteria on which the detection of a valid Alarm Indication Signal (AIS) is based. If zero, the criteria is less than three zeros in a two frame ...
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Advance Information Bit Name Functional Description 3 Unused Table 80 - Transmit Alarm Control Word (E1) (Page 1, Address 11H) Bit Name Functional Description Unused Unused. 5 HDLC0 HDLC0 ...
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MT9074 Bit Name Functional Description 1- 0 X2, X3 These bits are transmitted on the PCM 30 2048 kbit/sec. link in bit positions seven respectively, of time slot 16 of frame zero of every multiframe. X2 and X3 are normally ...
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Advance Information Bit Name Functional Description 2 RLBK Remote Loopback. If one, then all bipolar data received on RRTIP/ RRING are directly routed to TTIP/ TRING on the PCM 30 side of the MT9074. If zero, then this feature is ...
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MT9074 Bit Name Functional Description 4-0 Sa4- A one selects the corresponding Sa8 Sa bits of the NFA signal for kbits/sec. data link channel. Data link (DL) selection will function in termination mode only; ...
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Advance Information Bit Name Functional Description 7 RST Reset. When this bit is changed from zero to one the device will reset to its default mode. See the Reset Operation section for the default settings. 6 SPND Suspend Interrupts. If ...
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MT9074 Bit Name Functional Description 1 YIM Remote Signalling Multiframe Alarm Interrupt Mask. When unmasked (YI=1), an interrupt is initiated whenever a change of state of multiframe received unmasked masked. 0 SLPIM SLIP Interrupt unmasked ...
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Advance Information Bit Name Functional Description 2 PRBSOM PRBS Counter Interrupt. When unmasked (PRBSO = 1), an interrupt is initiated on overflow of PRBS counter (page 04H, address 10H) from FFH to 0H unmasked masked. ...
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MT9074 Bit Name 7 NRZ 6-4 TX2-0 3 REDBL 2-0 RES2-0 78 Functional Description NRZ Format Selection. Only used in the digital framer only mode (LIU is disabled). A one sets the MT9074 to accept a unipolar NRZ format input ...
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Advance Information Master Control 2 (Page-2) Master Control 2 (Page 02H) (E1) Address ( 10H (Table 96) Configuration Control Word 11H (Table 97) Custom Tx Pulse Enable 12H Reserved 13H ...
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MT9074 Bit Name Functional Description 7 T1/E1 E1 mode selection. when this bit is one, the device mode. 6-5 RSV Reserved. Must be kept at 0 for normal operation. 4 LIUEn LIU Enable.Setting this bit low enables ...
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Advance Information Bit Name Functional Description 7 RSV Reserved. Must be kept at 0 for normal operation. 6-0 CP6-0 Custom Pulse. These bits provide the capability for magnitude setting for the TTIP/TRING line driver A/D converter during the second phase ...
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MT9074 Master Status 1 (Page03H) (E1) Address ( 10H (Table 103) Synchronization Status Word 11H (Table 104) Alarm Status Word 1 12H (Table 105) Timer Status Word 13H (Table 106) ...
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Advance Information Bit Name Functional Description 7 SYNC Receive Basic Frame Alignment. SYNC indicates the basic frame alignment status (1 - loss acquired). 6 MFSYNC Receive Multiframe Alignment. MFSYNC indicates the multiframe alignment status (1 - loss; 0 ...
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MT9074 Bit Name Functional Description 1 RAIS Remote Alarm Indication Status. If one, there is currently a remote alarm condition (i.e., received A bit is one). If zero, normal operation. Updated on a non-frame alignment frame basis. 0 RCRS RAI ...
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Advance Information Bit Name Functional Description 7 RSLIP Receive Slip. A change of state (i.e., 1-to-0 or 0-to-1) indicates that a receive controlled frame slip has occurred. 6 RSLPD Receive Slip indicates that the last received frame slip resulted in ...
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MT9074 Bit Name Functional Description 7 - PD4 - Peak Detector 3 PD0 These five bits indicate the level of the received signal AMI pulses. PD4 PD3 PD2 PD1 PD0 ...
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Advance Information Bit Name Functional Description 7-4 RMAI1-4 Receive Multiframe Alignment Bits One to Four. These bits are received on the PCM 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero of ...
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MT9074 Master Status 2 (Page-4) Master Status 2 (Page 04H) (E1) Address ( 10H (Table 116) PRBS Error Counter 11H (Table 117) CRC Multiframe counter for PRBS 12H (Table 118) ...
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Advance Information Bit Name Functional Description PS7-0 This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 116 - PRBS Error Counter (Page 4, Address ...
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MT9074 Bit Name Functional Description 7 Unused 1-0 EC9-8 E bit Error Counter. The most significant 2 bits of the E bit error counter. Table 120 - E-bit Error Counter (Page 4, Address 14H) (E1) Bit Name ...
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Advance Information Bit Name Functional Description 3 LOSI Loss of When unmasked this interrupt bit goes high whenever a loss of signal (either analog - received signal below nominal or consecutive condition exists. 2 CEFI Consecutively ...
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MT9074 Bit Name Functional Description 7 FERRO Errored Framing Signal Counter Interrupt. When unmasked this interrupt bit goes high whenever the errored frame alignment signal counter changes from FFH to 00H. Reading this register clears this bit. 6 CRCO CRC ...
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Advance Information Bit Name Functional Description 7 FERROL Errored Frame Alignment Signal Counter Overflow Latch. This bit is set when the errored frame alignment signal counter overflows cleared after being read. 6 CRCOL CRC Error Latch. This bit ...
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MT9074 Per Channel Transmit Signalling (Pages 5 and 6) (E1) Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit Signalling Control Words for Channel Associated Signalling (CAS) channels and 18 ...
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Advance Information Bit Name A(n), Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM 30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where B(n), ...
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MT9074 Bit Name 7 TXMSG Transmit Message Mode. if high, the data from the corresponding address location of Tx message mode buffer is transmitted in the corresponding PCM 30 time slot. If zero, the data on DSTI is transmitted on ...
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Advance Information Per Channel Receive Signalling (Pages 9 and 0AH) (E1) Page 09H, addresses 10001 to 11111, and page 1AH addresses 10001 to 11111 contain the Receive Signalling Control Words for CAS channels and 18 to 32. ...
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MT9074 HDLC Control and Status (Page B for HDLC0 and Page C for HDLC1) Address Control (Write/Verify) 10H(Table 140) Address Recognition 1 11H(Table 141) Address Recognition 2 12H (Table TX FIFO 142/143) 13H(Table 144) HDLC Control 1 14H(Table 145) --- ...
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Advance Information Bit Name Functional Description ADR16-11 Address 16 - 11. A six bit address used for comparison with the first byte of the received address. ADR16 is MSB. 1 ADR10 Address 10. This bit is used ...
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MT9074 Bit Name Functional Description 7 ADREC When high this bit will enable address forces the receiver to recognize only those packets having the unique address as programmed in the Recognition Registers or if the address is an All call ...
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Advance Information Bit Name 7 INTGEN Interrupt Generated. Set to 1 when an interrupt (in conjunction with the Interrupt Mask Register) has been generated by the HDLC. This is an asynchronous event reset when the interrupt Register is ...
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MT9074 Bit Name Functional Description 7 INTSEL Interrupt Selection. When high, this bit will cause bit 2 of the Interrupt Register to reflect a TX FIFO underrun (TXunder). When low, this interrupt will reflect a frame abort (FA). 6 CYCLE ...
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Advance Information Bit Name Functional Description Ahead. Indicates a go-ahead pattern was detected by the HDLC receiver. This bit is reset after a read. 6 RxEOP End Of Packet Detected. This bit is set when an end ...
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MT9074 Bit Name Functional Description 7- TxCNT Transmit Byte Count Register. The 0s 7-0 Transmit Byte indicating the length of the packet about to be transmitted. When this register reaches the count of one, the next write to the Tx ...
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Advance Information Bit Name Functional Description 7-4 RSV These bits are reserved. 3 RxCLK Receive Clock. This bit represents the receiver clock generated after the RXEN control bit, but before zero deletion is considered. 2 TxCLK Transmit Clock. This bit ...
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MT9074 Bit Name Functional Description 7 --- Unused. 6-4 RFFS2-0 These bits select the RXFF (Rx FIFO Full) interrupt threshold level: RFF RFF RFF ...
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Advance Information Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Voltage at Digital Outputs 5 Current at Digital Outputs 6 Storage Temperature * Exceeding these values may cause permanent damage. ...
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MT9074 AC Electrical Characteristics -Timing Parameter Measurement Voltage Levels Characteristics 1 TTL Threshold Voltage 2 CMOS Threshold Voltage 3 Rise/Fall Threshold Voltage High 4 Rise/Fall Threshold Voltage Low Note 1: Timing for output signals is based on the worst case ...
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Advance Information DS t DSH CS R/W A0-A4 D0-D7 READ D0-D7 WRITE Note: DS and CS may be connected together. AC Electrical Characteristics Characteristics 1 RD low 2 RD High 3 CS Setup 4 CS Hold 5 Address Setup 6 ...
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MT9074 A0-A4 D0-D7 READ D0-D7 WRITE AC Electrical Characteristics - Transmit Data Link Timing (T1 mode) Characteristic 1 Data Link Clock Pulse Width 2 Data Link Setup 3 Data Link Hold TxDLCLK TxDL Figure 18 - Transmit ...
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Advance Information AC Electrical Characteristics - Transmit Data Link Timing (E1 mode) Characteristic 1 Data Link Clock Output Delay 2 Data Link Setup 3 Data Link Hold C4b TxDLCLK TxDL Figure 19 - Transmit Data Link Timing Diagram (E1 mode) ...
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MT9074 RxFP RxDLCLK RxDL Figure 21 - Receive Data Link Functional Timing (T1 mode) RxFP t RFD E1.5o RxDLCLK t RDD RxDL Figure 22 - Receive Data Link Diagram (T1 mode) AC Electrical Characteristics - Receive Data Link Timing (E1 ...
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Advance Information RxFP TIME SLOT 0 Bits 4,3,2,1,0 RxDLCLK RxDL RxDLCLK RxDL Figure 23 - Receive Data Link Functional Timing (E1 mode) E2o t RDC RxDLCLK t RDD RxDL Figure 24 - Receive Data Link Timing Diagram (E1 mode) AC ...
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MT9074 ST-BUS Channel 31 Bit Cells Bit 0 F0b C4b Figure 25 - ST-BUS Functional Timing Diagram ST-BUS Bit Bit Cell Stream F0b (Input) C4b (Input) All Input Streams All Output Streams Figure 26 - ST-BUS Timing Diagram (Input Clocks) ...
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Advance Information ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All Output Streams Figure 27 - ST-BUS Timing Diagram (Output Clocks) AC Electrical Characteristics - Multiframe Timing ( mode) Characteristic 1 Receive ...
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MT9074 DSTi Bit 7 Bit 6 Bit 5 Bit Cells F0b C4b (4.096 MHz) TxMF Figure 29 - Transmit Multiframe Functional Timing (T1 mode or E1 mode) F0b t MOD C4b (1) RxMF t MS (1) TxMF (1) Note : ...
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Advance Information C1.50 TxA/TxB Figure 31 - Transmit Digital Data Timing Diagram (LIU Disabled) AC Electrical Characteristics - Transmit Digital Framer Mode Characteristics 1 Transmit Clock Pulse Width 2 Transmit clock Pulse Width 3 Transmit Data Delay C1.5i RxA/B Figure ...
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MT9074 Frame Frame 12 1 Channel SBit Most Significant Bit (First) Frame Frame 15 0 Time Slot Most Significant Bit (First) Channel Channel 0 31 Most Significant Bit (First) 118 1.5 s • • • • • • • • ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...