CY7C1347 Cypress Semiconductor Corporation., CY7C1347 Datasheet
CY7C1347
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CY7C1347 Summary of contents
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... Pentium and Intel are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V and PowerPC™ All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... 100-Pin TQFP 14 15 CY7C1347/ 16 CY7C1347B CY7C1347 DDQ 76 V SSQ BYTE1 SSQ V 70 DDQ ...
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... J V DDQ DDQ DDQ Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 119-Ball BGA CY7C1347/CY7C1347B (128K x 36 ADSP CE A ADSC DQP ...
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... Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. 4 CY7C1347 , CE , and are also loaded into the ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ [31:0] output drivers ...
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... Burst Sequences The CY7C1347 provides a two-bit wraparound counter, fed that implements either an interleaved or linear burst se- [1:0] quence. The interleaved burst sequence is designed specifi- cally to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a lin- ear burst sequence. The burst sequence is user-selectable through the MODE input ...
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... CY7C1347 ADV OE DQ Write Hi-Z Read Hi-Z ...
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... Latch-Up Current .................................................... >200 mA Operating Range +150 C Ambient +125 C Range Temperature 0.5V to +4.6V Com’ + 0.5V DD Ind’l – + data when OE is active [31:0] [3:0] 8 CY7C1347 ...
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... MHz 1/t MAX CYC 10-ns cycle, 100 MHz Max Device Deselected Test Conditions MHz 3.3V 3.3V DDQ 9 CY7C1347 Min. Max. Unit 3.135 3.6 V 2.375 3.6 V 2.4 V 0.4 V 2 –0.3 0 – –5 ...
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... R=317 3.3V OUTPUT 2. GND R=351 INCLUDING JIG AND SCOPE (b) [11, 12, 13] -166 Min. Max. 6.0 1.7 1.7 2.0 0.5 3.5 1.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 [12, 13] 3.5 [12, 13] 0 [12] 3.5 is less than t and t is less than t . EOLZ CHZ CLZ 10 CY7C1347 [10] ALL INPUT PULSES 90% 90% 10% 10% 2.5 ns 2.5 ns (c) -133 -100 Min. Max. Min. Max. Unit 7.5 10 1.9 3.5 1.9 3.5 2.5 2.5 0.5 0.5 4.0 5.5 2.0 2.0 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2 ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 15. WDx stands for Write Data to Address X. Burst Write ADSP ignored with CE inactive CL 1 WD2 masks ADSP UNDEFINED = DON’T CARE 11 CY7C1347 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High ...
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... RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = DON’T CARE = UNDEFINED 12 CY7C1347 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... All chip selects need to be active in order to select the device Burst Read t ADSP ignored with ADH RD3 masks ADSP EOHZ See Note Out Out In = DON’T CARE = UNDEFINED 13 CY7C1347 Unselected Pipelined Read inactive 1 t DOH Out Out Out t CHZ ...
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... OE t CLZ Data In/Out 1a 2a Out Out t CO Back to Back Reads CYC CL CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out UNDEFINED = DON’T CARE 14 CY7C1347 WD2 WD3 WD4 t WEH D( DOH t CHZ ...
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... ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active DDZZ Three-state 15 CY7C1347 t ZZREC ...
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... CY7C1347B-166AC CY7C1347B-166BGC 133 CY7C1347-133AC CY7C1347B-133AC CY7C1347B-133BGC 100 CY7C1347-100AC CY7C1347B-100AC CY7C1347B -100BGC CY7C1347-100AI CY7C1347B-100AI Note: 22. Revision of the die is included in the part ordering information. blank --> First revision; B --> Second revision. Document #: 38-00727-C Package Name Package Type A101 100-Lead Thin Quad Flat Pack ...
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... Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 17 CY7C1347 51-85050-A ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1347 51-85115 ...