MAX9765ETJ+ Maxim Integrated Products, MAX9765ETJ+ Datasheet - Page 19

• Manufacturer Part Number: MAX9765ETJ+
• Description: IC AMP AUDIO .75W STER AB 32TQFN
• Manufacturer: Maxim Integrated Products
• Type: Class ABr

Specifications of MAX9765ETJ+

• Output Type: 2-Channel (Stereo) with Stereo Headphones
• Max Output Power X Channels @ Load: 750mW x 2 @ 4 Ohm; 65mW x 2 @ 16 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Depop, I²C, Input Multiplexer, Microphone, Mute, Short-Circuit and Thermal Protection, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

condition, the bus remains active. When a STOP con-
dition or incorrect address is detected, the
MAX9765/MAX9766 internally disconnects SCL from
the serial interface until the next START condition, mini-
mizing digital noise and feedthrough.
The MAX9765/MAX9766 recognize a STOP condition at
any point during the transmission except if a STOP con-
dition occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I
at least one clock pulse must separate any START and
STOP conditions.
A REPEATED START (S
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
master is writing to several I
want to relinquish control of the bus. The MAX9765/
MAX9766 serial interface supports continuous write
operations with or without an S
them. Continuous read operations require S
because of the change in direction of data flow.
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9765/MAX9766 generate an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX9765/MAX9766 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
Figure 3. 2-Wire Serial Interface Timing Diagram
SDA
SCL
750mW Audio Amplifiers with Headphone Amp,
t
HD, STA
CONDITION
START
______________________________________________________________________________________
r
may also be used when the bus
REPEATED START Conditions
t
LOW
r
) condition may indicate a
t
2
R
C devices and does not
Acknowledge Bit (ACK)
Early STOP Conditions
t
t
SU, DAT
HIGH
r
condition separating
Microphone Preamp, and Input Mux
t
F
t
HD, DAT
r
2
conditions
C format;
t
HD, STA
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9765/
MAX9766 wait for a START condition followed by its
slave address. The serial interface compares each
address value bit-by-bit, allowing the interface to power
down immediately if an incorrect address is detected.
The LSB of the address word is the Read/Write (R/W)
bit. R/W indicates whether the master is writing to or
reading from the MAX9765/MAX9766 (R/W = 0 selects
the write condition, R/W = 1 selects the read condition).
After receiving the proper address, the MAX9765/
MAX9766 issue an ACK by pulling SDA low for one
clock cycle.
The MAX9765 has a factory/user-programmed address
(Table 2). The MAX9766 has a factory-programmed
address: 1001011.
Figure 4. START/STOP Conditions
CONDITION
REPEATED
START
SDA
SCL
t
HD, STA
S
t
SP
t
SU, STO
Sr
CONDITION
STOP
Slave Address
t
BUF
CONDITION
START
P
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