AIF04ZPFC-01NNTL Astec Power, AIF04ZPFC-01NNTL Datasheet - Page 25

• Manufacturer Part Number: AIF04ZPFC-01NNTL
• Manufacturer: Astec Power

Technical Reference Note
AIF - PFC Power Factor
Correction Series
Interlock circuit between LD ENABLE and PF ENABLE (Continues from P.9, LD
ENABLE)
Initially the load is disabled and the LD ENABLE (pin 15) is at 0.4V (LOW). When the PFC power up sequence has
completed, the LD ENABLE voltage goes HIGH. And the LD ENABLE will stay high as long as Vin is above 175Vac or
Vout is above 250V, even if PF_ENABLE is in disable mode. If the application needs the LD_EN goes low when the
PF_EN is disable, please use the following interlock circuitry.
LD_EN goes low when PF_EN is set low (AIF04ZPFC-01L)
LD_EN goes low when PF_EN is set high (AIF04ZPFC-01NL)
MODEL : AIF -
PFC Series
March 2006 REVISION 09
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