HM538123BJ-7 HITACHI, HM538123BJ-7 Datasheet
HM538123BJ-7
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HM538123BJ-7 Summary of contents
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HM538123B Series 1 M VRAM (128-kword Description The HM538123B is a 1-Mbit multiport video RAM equipped with a 128-kword 256-word 8-bit SAM (serial access memory). asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes ...
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... HM538123B Series 3 variations of refresh (8 ms/512 cycles) -only refresh 5$6 -before- refresh &$6 5$6 Hidden refresh TTL compatible Ordering Information Type No. Access Time HM538123BJ HM538123BJ HM538123BJ HM538123BJ-10 100 ns 2 Package 400-mil 40-pin plastic SOJ (CP-40D) ...
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... Column address strobe &$6 Write enable :( / Data transfer/Output enable ' Serial clock SAM port enable 6( DSF Special function input flag QSF Special function output flag V Power supply CC V Ground connection HM538123BJ Series SI/ SI/O0 SI/ SI/O1 SI/ SI/O2 SI/ SI/ ...
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HM538123B Series Block Diagram A0 – A7 Column Address Buffer Input Data Control Input Buffer I/O0 – I/ – – A8 Row Address Refresh Buffer Counter Row Decoder 0 255 511 Memory Array 0 Serial Output ...
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Pin Functions 5$6 5$6 (input pin basic RAM signal active in low level and standby in high level. Row 5$6 address and signals as shown in table 1 are input at the falling edge of determine ...
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HM538123B Series I/O0 – I/O7 (input/output pins): I/O pins function as mask data at the falling edge of mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After ...
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Operation of HM538123B RAM Read Cycle ( / high &$6 edge of ) &$6 Row address is entered at the falling edge and column address at the 5$6 in standard DRAM. Then, when :( outputs through I/O pin. ...
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HM538123B Series High-Speed Page Mode Cycle ( / '7 High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling while is low. Its cycle time is one third of the random read/write cycle. ...
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Color Register Set Cycle RAS CAS Address Row WE DT/OE DSF Color Data I/O Set color register Block Write Cycle ( high, &$6 '7 falling edge of ) &$ block write cycle, 4 columns of data (4-word data ...
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HM538123B Series Color Register Set Cycle RAS CAS Row Address WE DT/OE DSF I/O Color Data *1 I/O WE I/O Mask Data Low High Don't care I/O Mask Data Low: Mask High: Non Mask Address Mask Data Column0 (A0 = ...
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Read Transfer Cycle ( high, &$6 '7 This cycle becomes read transfer cycle by driving . The row address data (256 5$6 synchronously at the rising edge of from SAM start address determined by column address. In read transfer cycle, ...
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HM538123B Series Write Transfer Cycle ( high, &$6 '7 Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the ...
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A8 A0 000000000 011111111 100000000 111111111 (Read transfer cycle) Figure 4 Example of Row Bit Data Transfer Memory Array AX8 = 0 Figure 5 Block Diagram for Split Transfer Split Write Transfer Cycle ( high, &$6 ...
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HM538123B Series RAS t (min) STS CAS Address DT/OE DSF 255 SC (127) Figure 6 Limitation in Split Transfer SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer ...
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Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) -before- (CBR) refresh cycle, and (3) Hidden ...
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HM538123B Series Recommended DC Operating Conditions ( +70°C) Parameter Symbol *1 Supply voltage Input high voltage Input low voltage V IL Notes: 1. All voltages referred –3.0 ...
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DC Characteristics ( +70°C, V HM538123B -6 Parameter Symbol Min Max Min Max Min Max Min Max Unit RAM Port -before- I — 50 &$6 CC5 refresh 5$6 current I — 100 — CC11 Data transfer I ...
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HM538123B Series AC Characteristics ( +70°C, V Test Conditions Input rise and fall time : 5 ns Output load : See figures Input pulse levels 3 Input timing reference levels : 0.8 V, ...
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Common Parameter Parameter Symbol Min Max Random read or write cycle t RC time precharge time t 5$6 RP pulse width t 5$6 RAS pulse width t &$6 CAS Row address setup time t ASR Row address hold time t ...
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HM538123B Series Read Cycle (RAM), Page Mode Read Cycle Parameter Symbol Min Max Access time from t 5$6 RAC Access time from t &$6 CAC Access time from t 2( OAC Address access time t AA Read command setup time ...
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Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle Parameter Symbol Min Max Write command setup time t WCS Write command hold time t WCH Write command pulse width t WP Write command to lead t 5$6 RWL ...
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HM538123B Series Read-Modify-Write Cycle Parameter Symbol Min Max Read-modify-write cycle time t RWC pulse width (read-modify- t 5$6 RWS write cycle) to delay time t &$6 :( CWD Column address to delay t :( AWD time to data-in delay time ...
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Flash Write Cycle, Block Write Cycle Parameter Symbol Min Max to data-in delay time t &$6 CDD to data-in delay time t 2( ODD Read Transfer Cycle Parameter Symbol hold time referenced #$ RDH hold time referenced ...
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HM538123B Series Read Transfer Cycle (cont) Parameter Symbol Min Max SC pulse width precharge time t SCP SC access time t SCA Serial data-out hold time t SOH Serial data-in setup time t SIS Serial data-in hold ...
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Pseudo Transfer Cycle, Write Transfer Cycle Parameter Symbol Min Max setup time referred 5$6 ES hold time referred 5 setup time referred to t 5$6 SRS to SC delay time t 5$6 ...
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HM538123B Series Split Read Transfer Cycle, Split Write Transfer Cycle Parameter Symbol Min Max Split transfer setup time t STS Split transfer hold time t RST referenced to 5$6 Split transfer hold time t CST referenced to &$6 Split transfer ...
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Serial Read Cycle, Serial Write Cycle Parameter Symbol Min Max Serial clock cycle time t SCC SC pulse width precharge width t SCP Access time from SC t SCA Access time from t 6( SEA Serial data-out ...
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HM538123B Series 16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. After read transfer cycle, if split read transfer cycle is executed without ...
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Early Write Cycle RAS t CAS t t ASR RAH Address Row I/O (Output I/O Mask Data (Input DTS DTH DT/ FSR RFH DSF Note: 1. ...
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HM538123B Series Read-Modify-Write Cycle RAS t RCD CAS t RAD t t ASR RAH Address Row I/O (Output I/O Mask Data (Input DTS DTH DT/ RFH ...
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Page Mode Write Cycle (Early Write) RAS t CSH t RCD CAS ASR RAH ASC Address Row Column WCS WE *1 I/O (Output I/O Mask Valid ...
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HM538123B Series 5$6 5$6 -Only Refresh Cycle RAS t CRP CAS t t ASR RAH Row Address t OFF1 I/O (Output) t CDD t I/O OFF2 (Input) t ODD t t DTH DTS DT/ FSR RFH DSF &$6 ...
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Hidden Refresh Cycle RAS t RCD CAS t RAD t t ASR t RAH t Address Row t RCS WE I/O (Output) t DZC I/O (Input) t DZO t t DTS DTH DT/ RFH FSR t FSC DSF ...
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HM538123B Series Color Register Set Cycle (Delayed Write) RAS CAS t t ASR RAH Address Row I/O (Output) I/O (Input) t DTS DT/ FSR RFH DSF Color Register Read Cycle RAS t CAS t t ...
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Flash Write Cycle RAS t CRP CAS Address WE t CDD t OFF1 I/O (Output) t OFF2 t ODD I/O (Input) t DTS DT/OE DSF Block Write Cycle RAS t CRP CAS Address WE t CDD t OFF1 I/O (Output) ...
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HM538123B Series Page Mode Block Write Cycle RAS t CSH t RCD CAS t t ASR t RAH ASC Column Row Address A2- I/O (Output I/O I/O Address ...
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Read Transfer Cycle (1) RAS t RCD CAS t RAD t t ASR RAH Address Row I/O (Output) t DTS DT/ FSR RFH DSF t SCC SC t SCA t SOH Valid Sout ...
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HM538123B Series Read Transfer Cycle (2) RAS t RCD CAS t RAD t t ASR RAH Address Row I/O (Output DTS DTH DT/ FSR RFH DSF t SRS ...
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Pseudo Transfer Cycle RAS t RCD CAS t t ASR RAH Address Row I/O (Output DTS DTH DT/ FSR RFH DSF t SEZ SRS t ...
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HM538123B Series Write Transfer Cycle RAS t RCD CAS t t ASR RAH Address Row I/O (Output) t DTS t DTH DT/ FSR RFH DSF SRS t ...
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Split Read Transfer Cycle RAS t CRP CAS t ASR Address Row OFF1 I/O (Output) t DTS DT/OE t FSR DSF Low SE t STS n SC 511 (n+255) (255) t SCA t SOH SI/O (Output) ...
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HM538123B Series Split Write Transfer Cycle RAS CAS t ASR Address Row OFF1 I/O (Output) t DTS DT/OE t FSR DSF Low SE t STS n SC 511 (n+255) (255) SI/O (Output SIS SIH ...
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Serial Read Cycle SE t SCC SCP SC t SCA t SOH SI/O Valid Sout Valid Sout (Output) Serial Write Cycle t SWH SE t SCC SIS SIH SI/O Valid Sin (Input) ...
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... HM538123B Series Package Dimensions HM538123BJ Series (CP-40D) 25.80 26.16 Max 40 1 0.74 1.30 Max 1.27 0.43 0.10 0.41 0.08 0.10 Dimension including the plating thickness Base material dimension 9.40 0.25 Hitachi Code CP-40D JEDEC — EIAJ Conforms Weight (reference value) 1.73 g Unit: mm ...
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... All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. ...
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HM538123B Series Revision Record Rev. Date Contents of Modification 1 Mar.18, 1994 Initial issue 2.0 Dec.8, 1994 Addition of figure 4: Example of row bit data transfer Addition of description about figure 4 for write transfer cycle 3.0 Apr. 24, ...