MAX3645EEE+T Maxim Integrated Products, MAX3645EEE+T Datasheet - Page 7

• Manufacturer Part Number: MAX3645EEE+T
• Description: IC AMP LIMITING 16-QSOP
• Manufacturer: Maxim Integrated Products
• Type: Limiting Amplifierr

Specifications of MAX3645EEE+T

• Applications: Data Quantizer, Optical Receivers
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. Functional Diagram
The external autozero capacitor (C
internal capacitance (C
stant of the DC offset correction loop. With C
(recommended), the -3dB frequency cutoff of the signal
path is typically 0.5kHz.
The external resistor R
ing stage. This gain setting controls the threshold at
which the power detector indicates an LOS condition.
Power detection is accomplished by rectifying and low-
pass filtering the data signal, then comparing it to the
programmed threshold voltage. A hysteresis of 2dB
prevents the LOS output from chattering when the input
signal is near the threshold.
The data outputs (DOUT+, DOUT-) and the loss-of-sig-
nal outputs (LOS+, LOS-) are PECL outputs. The equiv-
alent PECL output circuit is shown in Figure 4.
The appropriate value of R
the Loss-Of-Signal Threshold vs. R
Typical Operating Characteristics.
The lowpass filter of the power detector comprises a
20kΩ on-chip resistor (R
(C
Programming LOS Assert/Deassert Levels
SD
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
DIN+
DIN-
). The C
TH
Power Detector and LOS Indicators
SD
CSD
Applications Information
capacitor value determines the power-
_______________________________________________________________________________________
CAZ1
CORRECTION
TH
DETECTOR
Amplifier with Loss-of-Signal Detector
OFFSET
POWER
INT
C
SD
INT
sets the gain of the first limit-
), determines the time con-
) and an external capacitor
TH
CAZ2
PECL Output Buffer
LOS Time Constant
is determined by using
AZ
MAX3645
), in parallel with
TH
graph in the
AZ
= 0.1µF
LOS
LOS
DOUT+
DOUT-
DIS
detector time constant, which determines the LOS
assert/deassert time. With C
deassert time is in the range of 2.3µs to 80µs. This pro-
vides a long enough time constant to avoid false trig-
gering due to variations in mark density.
When the DIS input is forced high, the disable function
is enabled, which holds DOUT+ low and DOUT- high.
The disable function is used to prevent the data outputs
from toggling due to noise when no signal is present.
The LOS output can be connected to the DIS input for
automatic squelch.
The proper termination for a PECL output is 50Ω to
(V
can be used. For more information on PECL termina-
tions and how to interface with other logic families, refer
to Maxim Application Note HFAN-01.0: Introduction to
LVDS, PECL, and CML.
For best performance, use good high-frequency layout
techniques. Filter power supplies, keep ground con-
nections short, and use multiple vias where possible.
Power-supply decoupling should be placed close to
the V
fier and use controlled-impedance transmission lines to
interface with the outputs when possible.
Figure 3. Equivalent Data Input Circuit
CC
CC
DIN+
DIN-
- 2V), but other standard termination techniques
pins. Minimize the distance from the preampli-
V
CC
4.8kΩ
PECL Output Terminations
V
CC
STRUCTURES
- 0.87V
ESD
Layout Considerations
4.8kΩ
SD
Disable Function
= 1nF the assert/
V
CC
7