X24325 Xicor, X24325 Datasheet
X24325
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X24325 Summary of contents
Page 1
... The Programmable Hardware Write Protect feature allows the user to install the X24325 with WP tied to V program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register ...
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... the first three bits of the 8-bit slave address. This allows up to eight X24325’s to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V priate. If actively driven, they must be driven with CMOS levels (driven to V ...
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... The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. Therefore, the X24325 will be considered a slave in all applications. Figure 1. Data Validity SCL ...
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... X24325 will respond with an acknowl- edge after the receipt of each subsequent eight-bit word. In the read mode the X24325 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no stop condition is generated by the master, the X24325 will continue to transmit data ...
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... Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next three bits are the device select bits. A system could have up to eight X24325’s on the bus. The eight addresses are defined by the state of the S S inputs ...
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... X24325 Page Write The X24325 is capable byte page write opera- tion initiated in the same manner as the byte write operation, but instead of terminating the write cycle af- ter the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24325 will respond with an acknowl- edge ...
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... R/W bit set HIGH. This will be followed by an acknowledge from the X24325 and then by the eight-bit word. The read oper- ation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. ...
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... At the end of the address space (address 4095), the counter “rolls over” and the X24325 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. ...
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... X24325 WRITE PROTECT REGISTER The Write Protect Register (WPR) is located at the highest address, FFFh. Figure 11. Write Protect Register WPR (Addr = FFFh WPEN 0 0 BP1 BP0 WPR.1 = WEL – Write Enable Latch (Volatile Write enable latch reset, writes disabled 1 = Write enable latch set, writes enabled If WEL = 0 then “ ...
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... X24325 Block Protect Bits The Block Protect Bits BP0 and BP1 determine which blocks of the memory are write-protected: Table 1. Block Protect Bits Protected BP1 BP0 Addresses 0 0 None 0 1 C00h–FFFh 1 0 800h–FFFh 1 1 0000h–FFFh Table 2. Write Protect Status Table ...
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... X24325 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias X24325.......................................– +135 C Storage Temperature ........................– +150 C Voltage on any Pin with Respect to V .................................... –1V to +7V SS D.C. Output Current ..............................................5mA Lead Temperature (Soldering, 10 Seconds) ...... 300 C RECOMMENDED OPERATING CONDITIONS Temperature Min. Commercial 0 C Industrial –40 C Military – ...
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... X24325 A.C. CONDITIONS OF TEST Input Pulse Levels V CC Input Rise and Fall Times Input and Output Timing Levels A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol f SCL Clock Frequency SCL T Noise Suppression Time I Constant at SCL, SDA Inputs ...
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... BUS CAPACITANCE (pF) t HIGH t LOW HD:STA t HD:DAT t SU:DAT Min. Typ. X24325 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. ACK t WR STOP CONDITION SYMBOL TABLE WAVEFORM 6552 ILL F19 13 ...
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... X24325 PACKAGING INFORMATION HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) PIN 1 INDEX PIN 1 0.300 (7.62) REF. SEATING PLANE 0.150 (3.81) 0.125 (3.18) ...
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... X24325 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.004 (0.19) 0.050 (1.27) 0.010 (0.25 0.0075 (0.19) 0.250" 0.010 (0.25) ...
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... X24325 PACKAGING INFORMATION 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V 0 – 8 See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) Gage Plane Seating Plane .019 (.50) .029 (.75) Detail A (20X) ...
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... Temperature Range Blank = + – + – +125 C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC 14-Lead TSSOP X24325 8-Lead Plastic DIP Blank = 8-Lead SOIC (JEDEC 14-Lead TSSOP X Blank = 4.5V to 5.5V + 4.5V to 5.5V, – + 2.7V to 5.5V + 2.7V to 5.5V, – ...