T7633 Agere Systems, T7633 Datasheet

T7633

Manufacturer Part Number

T7633

Description

Manufacturer

Agere Systems

Datasheet

1.T7633.pdf (250 pages)

Current page: 1 of 250
Download datasheet (2Mb)

Introduction

This advisory applies to the T7633 Dual T1/E1 3.3 V Short-Haul Terminator as described in the May 1998

T7633 Dual T1/E1 3.3 V Short-Haul Terminator Advance Data Sheet (DS98-244TIC).

Microprocessor Timing Requirements

This section describes a modification to the microprocessor interface timing information to guarantee proper

function of the line interface clear on read status register, LIU_REG0, at address 400 and A00 (hex).

For clear on read (COR) register LIU_REG0 to clear, the chip select (CS) and address value (AD0—AD7 and

A8—A11, or A0—A11) must be active for either of the following intervals after the completion of the read (RD)

or data strobe (DS) pulse.

1. If present, two microprocessor clock (MPCK) cycles.

2. Two internal SYSCK cycles, if MPCK is not present.

Two internal SYSCK cycles, at 16 times the line rate, are equivalent to 81 ns for DS1 and 61 ns for CEPT. If

MPCK is present, this time interval can range from 61 ns to 667 ns depending upon the particular repetition

rate selected for MPCK. The microprocessor interface timing table from the T7633 advance data sheet is

shown in Table 1, Microprocessor Interface I/O Timing Specifications on page 2 with the revised timing incor-

ported in the table (notes * and †). The timing diagrams, which did not change, are shown in Figure 1—

Figure 8.

For the case where MPCK is not present, it is recommended that the hold time between the deassertion of RD

or DS and the deassertion of CS be at least 110 ns to provide a safety margin.

This requirement is not specified in the T7633 advance data sheet.

The framer portion of the terminator internally latches the decoded register address within its logic for clearing

the framer CORs, and it does not require this timing modification.

T7633 Device Advisory for Version 1.0 of the Device

33 MHz maximum.

3 MHz minimum.

The internal SYSCK is a clock at 16 times the line rate (24.704 MHz for DS1 or 32.768 MHz for CEPT).

Device Advisory

September 1999

Related parts for T7633

T7633 Summary of contents

Page 1

... T7633 Device Advisory for Version 1.0 of the Device Introduction This advisory applies to the T7633 Dual T1/E1 3.3 V Short-Haul Terminator as described in the May 1998 T7633 Dual T1/E1 3.3 V Short-Haul Terminator Advance Data Sheet (DS98-244TIC). Microprocessor Timing Requirements This section describes a modification to the microprocessor interface timing information to guarantee proper function of the line interface clear on read status register, LIU_REG0, at address 400 and A00 (hex). For clear on read (COR) register LIU_REG0 to clear, the chip select (CS) and address value (AD0— ...

Page 2

... T7633 Device Advisory for Version 1.0 of the Device Microprocessor Interface I/O Timing In modes 1 and 3, asserting ALE_AS signal low is used to enable the internal address bus. In modes 2 and 4, the falling edge of ALE_AS signal is used to latch the address bus. Table 1. Microprocessor Interface I/O Timing Specifications Symbol Configuration t1 Modes 1 & ...

Page 3

... If MPCK is not used (MPCK is inactive), then t40 must exceed two 16x line clock periods. A t40 of 110 ns is suggested. The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 1—8. Agere Systems Inc. T7633 Device Advisory for Version 1.0 of the Device (continued) Parameter ...

Page 4

... T7633 Device Advisory for Version 1.0 of the Device Microprocessor Interface I/O Timing (continued A[0:11] VALID ADDRESS R DTACK AD[0:7] Figure 1. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = A[0:11] VALID ADDRESS t5 R/W DS DTACK AD[0:7] Figure 2. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) 4 (continued t10 ...

Page 5

... A[8:11] VALID ADDRESS t5 R/W DS t24 DTACK t21 t22 AD[0:7] VALID ADDRESS Figure 4. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) Agere Systems Inc. T7633 Device Advisory for Version 1.0 of the Device (continued t10 t9 t25 t20 t8 t7 t17 VALID DATA t11 t12 t13 t14 ...

Page 6

... T7633 Device Advisory for Version 1.0 of the Device Microprocessor Interface I/O Timing (continued) CS t31 ALE t32 A[0:11] VALID ADDRESS RD t36 RDY AD[0:7] MPCK Figure 5. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) CS ALE A[0:11] VALID ADDRESS WR RDY AD[0:7] MPCK Figure 6. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) 6 (continued) ...

Page 7

... A[8:11] VALID ADDRESS WR t55 RDY t52 t53 VALID ADDRESS AD MPCK Figure 8. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) Agere Systems Inc. T7633 Device Advisory for Version 1.0 of the Device (continued) t31 t34 t50 t37 t36 t39 t38 t31 t44 t51 t37 t36 ...

Page 8

... B8ZS, HDB3, or ZCS coding consequence, this possible fault in the FLLOOP function should have minimal impact on T1 and E1 system applications of the T7633. If the case of an all-zeros data stream is used as a special system test or diagnostic condition, these devices may be forced into the above fault condition when the T7633 is in the FLLOOP state ...

Page 9

... September 1999 AY99-010PDH Replaces AY99-007T1E1 to Incorporate the Following Updates 1. Separate AY99-007T1E1 into two advisories: one applying to the T7630 and one applying to the T7633. This advisory (AY99-010PDH) applies to the T7633. 2. Page 8, added Asynchronous SYSCK and PLLCK with Jitter Attenuator in the Line Transmit Path section. ...

Page 10

... Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. ...

Page 11

... T7633 Device Advisory Describing Differences Between Version 1.0 and Version 2.0 of Device Introduction This advisory applies only to the T7633 Dual T1/E1 3.3 V Short-Haul Terminator, and it describes the differ- ences between the two versions of the device. Data Sheet Changes Table 148, Framer FDL Control Command Register (FRM_PR21) on page 189 of the May 1998 T7633 Dual T1/E1 3 ...

Page 12

Page 13

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Features The T7633 Dual T1/E1 Terminator consists of two independent, highly integrated, software-config- urable, full-featured short-haul transceiver/framers. The T7633 provides glueless interconnection from a T1/E1 line to a digital PCM system. Minimal external clocks are needed. Only a system clock/frame sync and a phase-locked line rate clock are required. Sys- ...

Page 14

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Contents Features ................................................................................................................................................................... 1 Power Requirements and Package.................................................................................................................... 1 T1/E1 Line Interface Features............................................................................................................................ 1 T1/E1 Framer Features ...................................................................................................................................... 1 Facility Data Link Features................................................................................................................................. 1 Microprocessor Interface.................................................................................................................................... 1 Applications ........................................................................................................................................................ 1 Feature Descriptions .............................................................................................................................................. 13 T1/E1 Line Interface Features.......................................................................................................................... 13 T1/E1 Framer Features .................................................................................................................................... 13 Facility Data Link Features............................................................................................................................... 14 User-Programmable Microprocessor Interface ................................................................................................ 14 Functional Description ............................................................................................................................................ 15 Pin Information ....................................................................................................................................................... 19 Line Interface Unit: Block Diagram ......................................................................................................................... 26 Line Interface Unit: Receive ...

Page 15

... DS1 Modes .....................................................................................................................................................124 CEPT Modes...................................................................................................................................................124 Receive Elastic Store ......................................................................................................................................124 Transmit Elastic Store .....................................................................................................................................124 Concentration Highway Interface (CHI) ................................................................................................................125 CHI Parameters ..............................................................................................................................................126 CHI Frame Timing...........................................................................................................................................129 CHI Offset Programming.................................................................................................................................132 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Table of Contents (continued) Page 3 ...

Page 16

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Contents JTAG Boundary-Scan Specification ..................................................................................................................... 135 Principle of the Boundary Scan ...................................................................................................................... 135 Test Access Port Controller............................................................................................................................ 136 Instruction Register ........................................................................................................................................ 138 Boundary-Scan Register ................................................................................................................................ 139 BYPASS Register........................................................................................................................................... 139 IDCODE Register ........................................................................................................................................... 139 3-State Procedures ........................................................................................................................................ 139 Microprocessor Interface ...................................................................................................................................... 140 Overview ........................................................................................................................................................ 140 Microprocessor Configuration Modes............................................................................................................. 140 Microprocessor Interface Pinout Definitions ...

Page 17

... Absolute Maximum Ratings ..................................................................................................................................228 Operating Conditions ............................................................................................................................................228 Handling Precautions ............................................................................................................................................228 Electrical Characteristics .......................................................................................................................................229 Logic Interface Characteristics........................................................................................................................229 Power Supply Bypassing ......................................................................................................................................229 Outline Diagram ....................................................................................................................................................230 144-Pin TQFP .................................................................................................................................................230 Ordering Information .............................................................................................................................................231 Index .....................................................................................................................................................................232 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Table of Contents (continued) Page 5 ...

Page 18

... Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing...................... 51 Figure 20. T1 Frame Structure ............................................................................................................................... 55 Figure 21. T1 Transparent Frame Structure........................................................................................................... 56 Figure 22. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ...................... 58 Figure 23. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe Structures............................................................................................................................................... 66 Figure 24 ...

Page 19

... Respectively) .......................................................................................................................................133 Figure 55. Receive CHI (RCHIDATA) Timing .......................................................................................................134 Figure 56. Transmit CHI (TCHIDATA) Timing .......................................................................................................134 Figure 57. Block Diagram of the T7633’s Boundary-Scan Test Logic...................................................................135 Figure 58. BS TAP Controller State Diagram........................................................................................................136 Figure 59. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................145 Figure 60. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................145 Figure 61. Mode 2— ...

Page 20

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Table Table 1. Pin Descriptions........................................................................................................................................ 20 Table 2. Digital Loss of Signal Standard Select ..................................................................................................... 28 Table 3. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) ................................. 29 Table 4. DS1 LIU Receiver Specifications.............................................................................................................. 30 Table 5. CEPT LIU Receiver Specifications ........................................................................................................... 31 Table 6. Transmit Line Interface Short-Haul Equalizer/Rate Control ..................................................................... 34 Table 7 ...

Page 21

... Table 54. Receive Status of Frame Byte ..............................................................................................................112 Table 55. HDLC Frame Format.............................................................................................................................115 Table 56. Receiver Operation in Transparent Mode .............................................................................................119 Table 57. Summary of the T7633’s Concentration Highway Interface Parameters ..............................................126 Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0.....................................................132 Table 59. Programming Values for TOFF[2:0] when CMS = 1 .............................................................................132 Table 60 ...

Page 22

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Table Table 101. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) ((610—611); (C10—C11)) ................................................................................................................ 174 Table 102. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13)) ................... 174 Table 103. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15)) ...................... 175 Table 104. ET Bursty Errored Seconds Counter (FRM_SR22— ...

Page 23

... Table 188. FDL Transmitter FIFO Register (FDL_PR4) (804; E04)......................................................................214 Table 189. FDL Transmitter Mask Register (FDL_PR5) (805; E05) .....................................................................214 Table 190. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) ..............................................215 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator List of Tables (continued) Page ...

Page 24

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Table Table 191. FDL Register FDL_PR7...................................................................................................................... 215 Table 192. FDL Receiver Match Character Register (FDL_PR8) (808; E08)....................................................... 215 Table 193. FDL Transparent Control Register (FDL_PR9) (809; E09) ................................................................ 216 Table 194. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A) ............................................................ 216 Table 195. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B ...

Page 25

... TR-TSY-000009(5/86), TSY-000170(1/ 93), GR-253-CORE(12/95), GR-499-CORE(12/95), GR-820-CORE(11/94), GR-1244-CORE(6/95). Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator GHz N-Channel, Laterally-Diffused, Enhancement T1/E1 Framer Features Framing formats: — Compliant with T1 standards ANSI T1.231 (1997), AT&T TR54016, AT&T TR62411 (1998). — Unframed, transparent transmission in T1 and E1 formats. — ...

Page 26

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Feature Descriptions (continued) T1/E1 Framer Features (continued) Signaling: — DS1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. — DS1: D4 superframe 2-state and 4-state per- channel robbed bit. — DS1: SLC -96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. ...

Page 27

... TRANSMIT LINE INTERFACE UNIT TRANSMIT (XLIU) FRAMER TRING[1—2] TND[1—2], TPD[1—2], TLCK[1—2] A[11:0] AD[7:0] CS Figure 1. T7633 Block Diagram (One of Two Channels) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator RECEIVE RECEIVE ELASTIC STORE FRAMER (2 FRAMES) UNIT TCHICK RECEIVE SIGNALING UNIT RLCK ...

Page 28

... Extraction and insertion of the facility data link in ESF, T1DM, SLC -96, or CEPT-E1 modes are provided through a four-port serial interface or through a microprocessor-accessed, 64-byte FIFO either with HDLC formatting or transparently. In the T7633’s SLC -96 or CEPT-E1 frame formats, a facility data link (FDL) is provided for FDL access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive framer’ ...

Page 29

... Intel 80188 (or 80X88) interface protocol with independent read and write signals or the Motorola MC680X0 or M68360 interface protocol with address and data strobe signals. The T7633 is manufactured using low-power CMOS technology and is packaged in an 144-pin thin quad flat pack (TQFP) with 20 mils lead pitch. ...

Page 30

... Figure 3. T7633 Block Diagram: Transmit Section (One of Two Channels LOSS OF TLCK ALL 1s SIGNAL (AIS) PULSE JITTER EQUALIZER ATTENUATION AND (OPTIONAL: WIDTH TRANSMIT OR CONTROLLER ...

Page 31

... Advance Data Sheet May 2002 Pin Information The package type and pin assignment for the T7633 (Terminator-II) is illustrated in Figure 4. 1 GRND LOFRMRLCK1 2 SYSCK1 3 PLLCK-EPLL1 4 DIV-RCHICK1 5 DIV-PLLCK1 6 PLLCK1 7 8 GRNDA1 RRING_RND1 11 RTIP_RPD1 VDDA1 14 GRNDX1 15 TRING1 VDDX1 16 17 TTIP1 18 GRNDX1 19 NC ...

Page 32

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Pin Information (continued) Table 1 shows the list of T7633 pins and a functional description for each. Table 1. Pin Descriptions Pin Symbol 36, 73, 109 GRND 2 38 LOFRMRLCK 3 35 SYSCK 4 34 PLLCK-EPLL 5 33 DIV-RCHICK 6 32 DIV-PLLCK 7 31 PLLCK 8 30 GRND ...

Page 33

... I indicates an internal pull-up. † After RESET is deasserted, the channel is in the default framing mode function of the DS1/CEPT pin. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Type* I Receive Bipolar Ring. Negative bipolar input data from the receive analog line isolation transformer. ...

Page 34

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol C1 C2 137 45 TND 136 46 TLCK 135 47 RLCK 134 49 RFRMCK 133 48 CKSEL 132 50 RFRMDATA 131 51 RFS 130 52 RSSFS 129 53 RCRCMFS 128 54 RFDLCK 127 55 RFDL 126 56 TCHICK 125 57 TCHIFS indicates an internal pull-up. ...

Page 35

... RCHIDATAB indicates an internal pull-up. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Type* O Transmit CHI Data. Serial output system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high- impedance state for all inactive time slots. O Transmit CHI Data B. Serial output system data at 2.048 Mbits/s, 4 ...

Page 36

... In the demultiplexed address mode, the address is transparent through the T7633 and is latched on the rising edge of the ALE_AS signal. Alternatively, in the demultiplex mode, this pin may be connected to ground to make the address transparent through the T7633 ...

Page 37

... R/W is low (write), the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to DS; when AS is low and R/W is high (read), the T7633 drives the data bus with the contents of the addressed register while DS is low. ...

Page 38

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Block Diagram The T7633 LIU diagram is shown in Figure 5. Only a single transceiver is shown here for illustration purposes. RALOS RTIP EQUALIZER SLICERS RRING FLLOOP (DURING LIU AIS) FLLOOP TDM (NO LIU AIS) LOTC TTIP TRANSMIT PULSE EQUALIZER ...

Page 39

... RPD input will be the receive data port. If DUAL = 0, then the receive framer’s bipolar violation count will increment by 1 whenever the internal LIU-to-framer RND_BPV signal is one. The bipolar violation count is incre- mented on the rising edge of the receive framer’s RLCK clock signal. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 27 ...

Page 40

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Receive Receive Line Interface Configuration Modes Receive Line Interface Unit (RLIU) Alarms Analog Loss of Signal (ALOS) Alarm. An analog signal detector monitors the receive signal amplitude and reports its status in the analog loss of signal alarm bit ALOS (register LIU_REG0, bit 0). Analog loss of signal is indicated (ALOS = 1) if the amplitude at the RRING and RTIP inputs drops below a voltage approximately 18 dB below the nominal signal amplitude ...

Page 41

... When B8ZS(DS1)/HDB3(E1) coding is not used (i.e., CODE = 0), any violations in the receive data (such as two or more consecutive rail) are indicated on the RND-LIU output. When B8ZS(DS1)/ HDB3(E1) coding is used (i.e., CODE = 1), the HDB3/B8ZS code violations, including BPVs, are reflected on the RND-LIU output. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) RPD/RND 0 ...

Page 42

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Receive T1/DS1 LIU Receiver Specifications During T1/DS1 operation, the LIU receiver will perform as specified in Table 4. Table 4. DS1 LIU Receiver Specifications Parameter Analog Loss of Signal: Threshold to Assert Threshold to Clear Hysteresis Time to Assert (ALTIMER = 0) 2 Receiver Sensitivity ...

Page 43

... Agere transformer 2795K or 2795J and components listed in Table 13. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Min Typ ...

Page 44

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Receive 100 T1.408/I.431(DS1)/G.824(DS1 1 Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator 32 (continued) GR-499-CORE (NON-SONET CAT II INTERFACES) I ...

Page 45

... Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) G.823,ETSI-300-011A1 100 1 k FREQUENCY (Hz) TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION) 100 1 k FREQUENCY ( TYPICAL ...

Page 46

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Transmit Output Pulse Generation The line interface transmitter accepts a line rate clock and NRZ data in single-rail mode (DUAL = 0) or positive and negative NRZ data in dual-rail mode (DUAL = 1) from the transmit framer unit or, optionally, the system interface. ...

Page 47

... LIU_REG4, bit 3) prevents the LOTC alarm from occurring at the activation and deactivation of RLOOP but allows the alarm to operate normally during the RLOOP active period. The reset default is PRLALM = 0. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued Because the transmit equalization bits are needed to determine ...

Page 48

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Transmit LIU Transmitter Alarms (continued) LIU Transmitter Driver Monitor (TDM) Alarm The transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit line transformer, and periods of no data transmission. The TDM alarm (register LIU_REG0, bit 2) is the OR’d func- tion of both faults and provides information about the integrity of the LIU transmitter signal path ...

Page 49

... Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 1.0 0 250 500 750 TIME (ns) Figure 10. DSX-1 Isolated Pulse Template Minimum Curve Normalized UI ns Amplitude –0.77 0 –0.05 –0.23 350 –0.05 –0.23 350 0.50 – ...

Page 50

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Transmit DSX-1 Transmitter Pulse Template and Specifications During DS1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in Table 8. Table 8. DS1 Transmitter Specifications Parameter 1 Output Pulse Amplitude at DSX Output Pulse Width at Line Side of ...

Page 51

... MHz to 3.072 MHz 2 Return Loss kHz to 102 kHz 102 kHz to 3.072 MHz 1.With the line circuitry specified in Table 13, measured at the transformer secondary. 2.Using Agere transformer 2795K or 2795J and components in Table 13. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Min Typ Max 2.13 2.37 2.61 2 ...

Page 52

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Jitter Attenuator A selectable jitter attenuator is provided for narrow-bandwidth jitter transfer function applications. When placed in the LIU receive path, the jitter attenuator provides narrow-bandwidth jitter filtering for line-synchronization. The jitter attenuator can also be placed in the LIU transmit path to provide clock smoothing for applications such as synchro- nous/asynchronous demultiplexers ...

Page 53

... LIU transmit path by setting JAT = 1 (register LIU_REG3, bit 1). When JAR = 1 and JAT = 1 or when JAR = 0 and JAT = 0, the jitter attenuator is disabled. Note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. The reset default case is JAR = JAT = 0. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued ...

Page 54

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Jitter Attenuator 100 T1.408/I.431(DS1)/G.824(DS1 1 Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator 42 (continued) GR-499-CORE (NON-SONET CAT II INTERFACES) I ...

Page 55

... Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) G.823,ETSI-300-011A1 100 1 k FREQUENCY (Hz) I.431, G.735-9 WITH JITTER REDUCER ETSI-300-011 ETSI TBR12/13 JABW0 = 1 100 1 k FREQUENCY (Hz) TYPICAL ...

Page 56

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Loopbacks The LIU has independent loopback paths that are activated using LOOPA and LOOPB control bits (register LIU_REG5, bits shown in Table 10. The locations of these loopbacks are illustrated in Figure 5, Block Diagram of Line Interface Unit: Single Channel, on page 26. ...

Page 57

... CDR = 0. The equalizer plus slicer delay is nearly 0 UI delay. The jitter attenuator delay is nominally 33 UI but can be 2 UI—64 UI depending on state. The digital phase-locked loop used for timing recovery has 8 UI delay. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 45 ...

Page 58

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator SYSCK Reference Clock The LIU requires an externally applied clock, SYSCK pins 3 and 35, for the clock and data recovery function and the jitter attenuation option. SYSCK must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock such as from an external system oscillator or system clock for proper operation. It must not be derived from any recovered line clock (i ...

Page 59

... No activity such as microprocessor read/write should be performed during this period. The device will be operational 2.7 ms after the deactivation of the hardware reset pin. Issuing an LIU software restart (LIU_REG2 bit 5 (RESTART does not impact the clock synthesizer circuit. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 12 – 1) line clock periods, or 1.3 ms for DS1 and ...

Page 60

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit: Line Interface Networks The transmit and receive tip and ring connections provide a matched interface to the line cable when used with a proper matching network. The diagram in Figure 16 shows the appropriate external components to interface to the cable for a single transmit/receive channel. The component values are summarized in Table 13, based on the spe- cific application ...

Page 61

... Approximately 0.3 V—2.0 V peak. † Approximate pulse voltage source (peak). Mode Peak DS1 1.6 CEPT Option 1 2.3 Option 2 2.1 120 2.3 Figure 17. T7633 Line Interface Unit Approximate Equivalent Analog I/O Circuits Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued —1.5 TRANSMITTER OUTPUT 1 — ...

Page 62

... LIU-Framer Interface LIU-Framer Physical Interface The transmit framer-LIU interface for the T7633 consists of the TND, TPD, and TLCK pins. In normal operations, TND, TPD, and TLCK are directly connected to the transmit line interface and the TPD, TND, and TLCK pins are driven from the transmit framer. The receive framer-LIU interface for the T7633 consists of the RPD, RND_BPV, and RLCK internal signals ...

Page 63

... TLCK TND, TPD RLCK t6 RND, RPD t8 RFRMCK Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) t1 t1-DS1 t1-CEPT t2f-r t2r-f: t2f-r: PLLCK TO TLCK DELAY = 50 ns t3-DS1 = 648 ns t3 t3-CEPT = 488 ns ...

Page 64

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator LIU-Framer Interface (continued) Interface Mode and Line Encoding Single Rail The default mode for the LIU-framer interface is single-rail, register LIU_REG3 bit 3 (DUAL and register FRM_PR8 bit bit and bit the single-rail terminator mode (FRAMER = 1), the LIU bipolar encoder and decoder may be enabled by setting register LIU_REG3 bit 2 (CODE ...

Page 65

... B represents an inserted pulse conforming to the AMI rule. Table 16. DS1 B8ZS Encoding Bit Positions 1 2 Before B8ZS 0 0 After B8ZS 0 0 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 00000000 01010000 00000010 01010010 00000010 01010000 (data time slot remains clear ...

Page 66

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator LIU-Framer Interface (continued) CEPT: High-Density Bipolar of Order 3 (HDB3) The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). HDB3 uses a substitution code that acts on strings of four 0s. The substitute HDB3 codes are 000V and B00V, where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule defined in ITU Rec ...

Page 67

... Mbits/s T1 data rate. DS1 frames are bundled together to form superframes or extended super- frames. FRAME 1 FRAME 2 FRAME 1 FRAME 2 F BIT TIME SLOT Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Bit Rate (Mbits/s) 1.544 3.152 6.312 44.736 274.176 FRAME 3 FRAME 23 FRAME 11 TIME SLOT 2 ...

Page 68

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) T1 Framing Structures (continued) Transparent Framing Format The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system interface must be programmed such that the stuffed time slots are 13, 17, 21, 25, and 29 (FRM_PR43 bits 2— ...

Page 69

... Signaling option none uses bit 8 for traffic data. 5. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled. The receive framer uses both the F Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Bit Used in Each Time Slot Signal Traffic ...

Page 70

... TFDLCK TFDL RFDLCK RFDL Figure 22. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections SLC -96 Frame Format SLC -96 superframe format consists of 12 DS1 frames similar to D4. The F F pattern uses that same structure as D4 but also incorporates a 24-bit data link word as shown below. ...

Page 71

... D S — line-switch bit — line-switch bit Spoiler bit 4 24 (rightmost bit) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Bit Value ...

Page 72

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) T1 Framing Structures (continued) Table 22. SLC -96 Line Switch Message Codes Switch line B transmit and receive Switch line B transmit and receive ...

Page 73

... The ESF format allows for in-service error detection and diagnostics on T1 circuits. ESF format consist of 24 fram- ing bits: 6 for framing synchronization (2 kbits/s); 6 for error detection (2 kbits/s); and 12 for in-service monitoring and diagnostics (4 kbits/s). Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Bit Use in Each Time Slot 4 ...

Page 74

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) T1 Framing Structures (continued) Cyclic redundancy checking is performed over the entire ESF data payload (4,608 data bits, with all 24 framing bits ( CRC-6) set to 1 during calculations). The CRC-6 bits transmitted in ESF will be determined as follows: ...

Page 75

... ESF Frame and superframe alignment is established simultaneously using the F bit. Alignment is established when 24 consecutive F frame/superframe alignment is established, the CRC-6 receive monitor is enabled. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alignment Procedure frame position as the starting point, frame alignment is established when T and F ...

Page 76

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) T1 Robbed-Bit Signaling To enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0. Robbed-bit signaling, used in either ESF or SF framing formats, “robs” the eighth bit of the voice channels of every sixth (6th) frame. The signaling bits are designated and D, depending on the signaling format used. The robbed-bit signaling format used is defined by the state of the F and G bits in the signaling registers (see DS1: Robbed-Bit Signaling on page 85) ...

Page 77

... Table 29. 16-State Signaling Format Transmit Signaling Register Settings SLC -96 Signaling States State 0 State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator ...

Page 78

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Struc- tures As defined in ITU Rec. G.704, the CEPT 2.048 frame, CRC-4 multiframe, and channel associated signaling multi- frame structures are illustrated in Figure 23. ...

Page 79

... G.706 Annex C. Bits Sa4—Sa8, where these are not used, should be set links crossing an international border. 5. MSB = most significant bit and is transmitted first. 6. LSB = least significant bit and is transmitted last. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Bit 1 Bit 2 Bit 3 Bit 4 ...

Page 80

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT 2.048 Basic Frame Structure Transparent Framing Format The transmit framer can be programmed to transparently transmit 256 bits of system data to the line. The transmit framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Framer Reset and Transparent Mode Control Register (FRM_PR26) on page 192) ...

Page 81

... The absence of the frame alignment signal in the following frame detected by verifying that bit 2 of the basic frame frame For the second time, the presence of the correct frame alignment in the next frame Failure to meet above will initiate a new basic frame search in frame Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 69 ...

Page 82

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT Time Slot 0 CRC-4 Multiframe Structure The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy check-4 (CRC-4) procedure as detailed below. The allocation of bits 1— ...

Page 83

... Optionally, if LTS0MFA monitoring in the performance counters is enabled, by setting registers FRM_PR14 through FRM_PR17 bit then these counts are incremented once per second for the duration of the LTS0MFA state. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued the polynomial representation of the submultiframe N – 1. ...

Page 84

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms Several optional algorithms exist in the receive framer. These are selected through programming of register FRM_PR9. CRC-4 Multiframe Alignment Algorithm with 8 ms Timer The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition ...

Page 85

... START CRC-4 PERFORMANCE MONITORING: • SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4 CRC-4 YES COUNT > 914 IN 1 SECOND OR LFA = 1? Figure 25. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator YES NO YES INTERNAL 100 ms TRX = 1 ...

Page 86

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms CRC-4 Multiframe Alignment Search Algorithm with 400 ms Timer The CRC-4 multiframe alignment with 400 ms timer mode is enabled by setting FRM_PR9 to 0XXX1XX1 (binary). This receive CRC-4 multiframe reframe mode is the modified CRC-4 multiframe alignment algorithm described in ITU Rec ...

Page 87

... COUNT > 914 YES IN 1 SECOND OR LFA = 1? Figure 26. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator PRIMARY BFA SEARCH? YES NO CAN CRC-4 MFA BE FOUND ...

Page 88

... Table 32 illustrates the CAS multiframe of time slot 16. The T7633 can be programmed to force the transmitted line CAS multiframe alignment pattern to be transmitted in the FAS frame by selecting the PCS0 option or in the NOT FAS frame by selecting the PCS1 option ...

Page 89

... Ei = IRSM per-channel control bits. X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2. Ai—Di = time slot 16 channel associated signaling bits yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition). M Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued ...

Page 90

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Frame Formats (continued) CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe alignment state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multiframe 4-bit all-zero patterns is received with an error ...

Page 91

... CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can state of LFA and LTS0MFA state of LTS0MFA only, but cannot state of LFA only. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 3 if FRM_PR28 bit ...

Page 92

... The receive Sa data is present at: A. The Sa received stack, registers FRM_SR54—FRM_SR63, if the T7633 is programmed in the Sa stack mode. B. The system transmit interface. The status of the received Sa bits and the received Sa stack is available in status register FRM_SR4. The transmit and receive Sa bit for the FDL can be selected by setting register FRM_PR43 bit 0— ...

Page 93

... LOFRMRLCK being asserted. TFDLCK TFDL RFDLCK RFDL Figure 27. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued t10 t11 t8: TFDLCK CYCLE = 250 s t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns ...

Page 94

... CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous to the transmit CRC-4 multiframe structure. On the receive side, the T7633 indicates that it has received data in the receive Sa stack, register FRM_SR54— FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system then has about read the contents of the stack before it is updated again (old data lost) ...

Page 95

... Figure 28. Transmit and Receive Sa Stack Accessing Protocol Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) SYSTEM ACCESS Sa STACK INTERVAL 1 FRAME CRC-4 DOUBLE MULTIFRAME: 32 FRAMES INTERNAL Sa STACK UPDATE INTERVAL THE INTERNAL TRANSMIT Sa STACK IS UPDATED FROM THE FRAMER UNIT’S 10-byte TRANSMIT STACK CONTROL REGISTERS DURING THIS 1-FRAME INTERVAL ...

Page 96

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator CEPT Time Slot 0 FAS/NOT FAS Control Bits NOT FAS Sa Stack Source and Destination Interrupts indicating the transmit Sa stack or the receive Sa stack are ready for system access are available, see register FRM_SR4 bit 6 and bit 7. CEPT Time Slot 16 X0—X2 Control Bits Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0— ...

Page 97

... DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled. 1. All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDATA stream are ignored. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 85 ...

Page 98

... Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system inter- face. Table 36 illustrates the ASM format for T1 stuffed channels used by the T7633. The stuffed data byte contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is ignored. ...

Page 99

... Figure 29. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode TLCK TFS TPD (SINGLE TS1 RAIL) Figure 30. Timing Specification for TFS, TLCK, and TPD in DS1 Mode Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 125 s BIT 0 BIT 1 TIME SLOT 1 125 s TS2 TS24 5-6290(F)r ...

Page 100

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Auxiliary Framer I/O Timing RFRMCK RFS RFRMDATA BIT 8 TIME SLOT 31 DATA VALID Figure 31. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode RFRMCK RFS RSSFS RFRMDATA TS0 OF THE FRAME AFTER THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000) Figure 32 ...

Page 101

... Figure 33. Timing Specification for RCRCMFS in CEPT Mode TLCK TFS TPD (SINGLE TS0 OF FRAME X RAIL) Figure 34. Timing Specification for TFS, TLCK, and TPD in CEPT Mode Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued 125 s TS0 OF FRAME #0 OF MULTIFRAME 5-6296(F)r.5 TS0 OF FRAME 5-6297(F)r.5 ...

Page 102

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Auxiliary Framer I/O Timing TFS 11 CLOCK CYCLES TLCK TSSFS TPD (SINGLE RAIL) Figure 35. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode TLCK TFS 1 ms TCRCMFS TPD (SINGLE RAIL) TS0 OF FRAME #0 OF MULTIFRAME Figure 36. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode ...

Page 103

... The red alarm indicates that the receive frame alignment for the line has been lost and the data cannot be properly extracted. The red alarm is indicated by the loss of frame condition for the various framing formats as defined in Table 38. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator 5-6563(F) 91 ...

Page 104

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Alarm Definition (continued) Table 38. Red Alarm or Loss of Frame Alignment Conditions Framing Format Number of Errored Framing Bits That Will Cause a Red Alarm (Loss of Frame D4 2 errored frame bits (F 2 errored F T SLC -96 2 errored frame bits (F ...

Page 105

... After a reset, the read and write pointers of the receive path elastic store will be set to a known state. PLLCK LOPLLCK RCHICK Figure 38. Timing for Generation of LOPLLCK (Pin 39/143) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Remote Frame Alarm Format 250 s 250 ...

Page 106

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Alarm Definition (continued) 7. Received bipolar violation errors alarm, FRM_SR3 bit 0. This alarm indicates any bipolar decoding error or detection of excessive zeros. 8. Received excessive CRC errors alarm, FRM_SR3 bit 3. In ESF, this alarm is asserted when 320 or more CRC-6 checksum errors are detected within a one second interval ...

Page 107

... Table 41. Sa6 Bit Coding Recognized by the Receive Framer Code First Receive Bit (MSB) Sa6_8 1 hex Sa6_A 1 hex Sa6_C 1 hex Sa6_E 1 hex Sa6_F 1 hex Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Last Received Bit (LSB ...

Page 108

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Alarm Definition (continued) Table 42 defines the three 4-bit Sa6 codes that are always detected synchronously to the CRC-4 submultiframe structure, and are only used for counting NT1 events. Table 42. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer ...

Page 109

... CEPT with CRC-4 (NT1) Any Sa6 = 001x (binary) code event within a one CEPT with CRC-4 (NT1 remote) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Definition Any bipolar violation more consecutive zeros Any BPV, code violation, or any 8-bit interval with no ...

Page 110

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Event Counters Definition (continued) Table 44. Event Counters Definition (continued) Error Event Functional Mode Bursty Errored DS1: non ESF Second Events DS1: ESF CEPT without CRC-4 CEPT with CRC-4 (ET1) Greater than 1 but less than 915 CRC-4 errors within ...

Page 111

... Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to 101A where Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) , where the binary address of the selected time slot ...

Page 112

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Loopback and Transmission Modes 6. The PLLB mode loops the received line data and clock back to the transmit line while inserting (replacing) the facility data link in the looped back data. Two variations of the payload loopback are available. In the pass through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and CRC bits are looped back to the line transmit data ...

Page 113

... ES (3) SINGLE TIME-SLOT SYSTEM LOOPBACK FRAMER LINE ES TRANSMIT LINE TS-X IN SYSTEM TS-X AND SYSTEM TS-0 (5) CEPT NAILED-UP BROADCAST TRANSMISSION Figure 40. Loopback and Test Transmission Modes Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) AIS LINE SYSTEM TRANSMIT PROGRAMMABLE IDLE CODE SYSTEM LINE LOOPBACK TS-X ...

Page 114

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Line Test Patterns Test patterns may be transmitted to the line through either register FRM_PR20 or register FRM_PR29. Only one of these sources may be active at the same time. Signaling must be inhibited while sending these test patterns. Transmit Line Test Patterns—Using Register FRM_PR20 The transmit framer can be programmed through register FRM_PR20 to transmit various test patterns ...

Page 115

... Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued #13 Register FRM_PR69 Bit 7 Bit 6 Bit 5 Bit ...

Page 116

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Line Test Patterns (continued) Receive Line Pattern Monitor—Using Register FRM_SR7 The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed pat- terns, and indicates detection in register FRM_SR7 bit 6 and bit 7. ...

Page 117

... To select a pattern or change the pattern to be detected, the following programming sequence must be followed. DBLKSEL (register FRM_PR70 bit 2) is set to 0. The new pattern to be detected is selected by setting register FRM_PR70 bit 7—bit 4 to the desired value. DBLKSEL (register FRM_PR70 bit 2) is set to 1. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 105 ...

Page 118

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Alarms and Performance Monitoring Automatic and On-Demand Commands Various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. After reset, all automatic transmissions are disabled. The user can enable the automatic or on-demand actions by set- ting the proper bits in the automatic and on-demand action registers as identified below in Table 48 ...

Page 119

... Transmit Line Time Slot 16 CEPT Enable Loopback All Framer Software Reset All Framer Software Restart All Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Action bit in frame Bit 2 of all time slots = 0 Bit 6 in time slot Pattern of 1111111100000000 in ...

Page 120

... TFDL RFDLCK RFDL Figure 43. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections In the ESF frame format, automatic assembly and transmission of the performance report message (PRM) as defined in both ANSI T1.403-1995 and Telcordia Technologies TR-TSY-000194 Issue 1, 12—87 is managed by the receive framer and transmit FDL sections ...

Page 121

... ANSI FDL status register FDL_SR3 when the entire code is received. 3. The minimum number of times a valid code must be received before it is reported can be programmed from using register FDL_PR0 bit 4—bit 7. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) RECEIVE FDL ...

Page 122

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) Receive Facility Data Link Interface The received ANSI FDL status byte, register FDL_SR3, has the following format. Table 50. Receive ANSI Code Receive ANSI Performance Report Messages (PRM) As defined in ANSI T1.403, the performance report messages consist of 15 bytes, starting and ending with an HDLC flag ...

Page 123

... Variable 7, 8 Variable 9, 10 Variable 11, 12 Variable 13, 14 Variable 15 01111110 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Definition CRC Error Event 5 10 100 CRC Error Event 319 320 1 (FE will = 0) 1 (SE will = 0) 1 Slip Event 1 Reserved ...

Page 124

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) Receive Facility Data Link Interface Receive HDLC Mode This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. ...

Page 125

... FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF status byte. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) 113 ...

Page 126

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) Transmit Facility Data Link Interface The FDL interface of the transmit framer is shown in Figure 45, indicating the priority of the FDL sources. The remote frame alarm, enabled using register FRM_PR27, is given the highest transmission priority by the transmit framer ...

Page 127

... Whenever five 1s occur between flags bit is automatically inserted after the fifth 1, prior to transmission of the next bit. On the receive side, if five successive 1s are detected followed the 0 is assumed to have been inserted and is deleted (bit destuffing). Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Frame Check ...

Page 128

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) HDLC Operation (continued) 1 Flags All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automatically sends two flags between frames. If the chip-configuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the 1s idle byte (11111111) is sent between frames if no data is present in the FIFO ...

Page 129

... FTFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued ...

Page 130

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) HDLC Operation (continued) Using the Transmitter Status and Fill Level The transmitter-interrupt level bits, register FDL_PR3 bit 0—bit 5, allow the user to instruct the FDL HDLC block to interrupt the host processor whenever the transmitter has a predetermined number of empty locations. The number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts ...

Page 131

... No data to receive FIFO until match is detected Match user-defined character, but only on octet boundary. Boundary based on first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO until match is detected. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Receiver Operation 119 ...

Page 132

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Facility Data Link (FDL) Diagnostic Modes Loopbacks The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. The local loopback mode is selected when register FDL_PR1 bit 1 (FLLB) is set to 1. The remote loopback is selected when register FDL_PR1 bit 0 (FRLB) is set to 1 ...

Page 133

... The transmitter should be disabled. The receiver can be disabled or, if desired, enabled. Received data is sent as usual to the receive FIFO if the receiver is enabled. XMIT HDLC FDL BLOCK XMIT FIFO RCVR FIFO RCVR HDLC FDL BLOCK Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) XMIT HDLC RCVR HDLC Figure 47. Remote Loopback Mode TFDL FDL XMIT ...

Page 134

... As such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. The block diagram of the T7633 phase detector circuitry is shown in Figure 48 on page 123. The T7633 uses elas- tic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2 ...

Page 135

... INTERNAL_XLCK TLCK TRANSMIT FRAMER TPD, TND BUFFER OVERRUN BUFFER UNDERRUN WRITE ADDRESS RPD, RND RECEIVE FRAMER RLCK INTERNAL_RLCK Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) EXTERNAL CIRCUIT DIV-PLLCK PLLCK-EPLL PLLCK DIGITAL DIVIDER PHASE CIRCUIT DETECTOR TRANSMIT READ ADDRESS WRITE ADDRESS ...

Page 136

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer-System (CHI) Interface DS1 Modes The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 DS1 (1 ...

Page 137

... FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA interface to a high-impedance state for the interval of the disabled time slots. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator ® TDM highway interfaces, with no glue logic. Configured via the highway ...

Page 138

... Concentration Highway Interface (CHI) CHI Parameters The CHI parameters that define the receive and transmit paths are given in Table 57. Table 57. Summary of the T7633’s Concentration Highway Interface Parameters Name HWYEN Highway Enable (FRM_PR45 bit 7 this bit enables the transmit and receive concentration highway interfaces ...

Page 139

... May 2002 Concentration Highway Interface (CHI) CHI Parameters (continue) Table 57. Summary of the T7633’s Concentration Highway Interface Parameters (continued) Name TTSE31—TTSE0 Transmit Time-Slot Enable 31—0 (FRM_PR49—FRM_PR52). These bits define which transmit CHI time slots are enabled enables the TCHIDATA or TCHI- DATAB time slot forces the CHI transmit highway time slot to be 3-stated. RTSE31— ...

Page 140

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Concentration Highway Interface (CHI) CHI Parameters (continued) Table 57. Summary of the T7633’s Concentration Highway Interface Parameters (continued) Name TLBIT Transmit Least Significant Bit First (FRM_PR47 bit 7). When TLBIT = 0 (the default mode), the most significant bit (bit 0) of each time slot is transmitted first. ...

Page 141

... FRAME 1 RCHIDATA * The position of the stuffed time is controlled by register FRM_PR43 bit 0—bit 2. Figure 49. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary)) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 125 s FRAME 1 24 VALID TIME SLOTS 24 VALID TIME SLOTS ...

Page 142

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Concentration Highway Interface (CHI) CHI Frame Timing (continued) CHI Timing with CHIDTS Enabled Figure 50 illustrates the CHI frame timing when CHIDTS is enabled (registers FRM_PR65 bit 1 (TCHIDTS) and FRM_PR66 bit 1 (RCHIDTS and ASM is disabled (register FRM_PR44 bit 2 (ASM) = 0). In the CHIDTS mode, valid CHI payload time slots are alternated with high-impedance intervals of one time-slot duration ...

Page 143

... DATA SIGNALING RCHIDATA 16 bits 1 TIME SLOT * High-impedance state for TCHIDATA and not received (don’t care) for RCHIDATA. Figure 52. CHI Timing with ASM and CHIDTS Enabled Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) 125 s FRAME 1 SIGNALING 0 DATA 31 FRAME HIGH IMPEDANCE ...

Page 144

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Concentration Highway Interface (CHI) CHI Offset Programming To facilitate bit offset programming, two additional internal parameters are introduced: CEX is defined as the clock edge with which the first bit of time slot 0 is transmitted; CER is defined as the clock edge on which bit 0 of time slot 0 is latched ...

Page 145

... RCE = 0, ROFF[2:0] = 000, RBYOFF[6:0] = 0000000, RLBIT = 0. CHICK TCHIFS, RCHIFS HIGH IMPEDANCE TCHIDATA: TCE = 1 RCHIDATA: RCE = 0 Figure 54. CHI TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 1 (CEX = 3 and CER = 6, Respectively) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) CHIFS IS SAMPLED ON THIS EDGE CEX = 3 HIGH IMPEDANCE ...

Page 146

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Concentration Highway Interface (CHI) CHI Offset Programming (continued) Figure 55 and Figure 56 illustrate the CHI timing. RCHICLK t14S RCHIFS t15S RCHIDATA Note: For case illustrated, RFE = 0, and RCE = 0. TCHICLK t14S TCHIFS TCHIDATA Note: For case illustrated, TFE = 0 and TCE = 0. ...

Page 147

... The main component is the BS register that links all the chip pins to a shift register by means of special logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the T7633 (the mode multiplexer of the BS output cells may be shared). Figure 57 illustrates the block diagram of the T7633’s BS test logic. ...

Page 148

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator JTAG Boundary-Scan Specification Test Access Port Controller The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST signals and by the previous state. The state change always take place when the TCK edge rises ...

Page 149

... This temporary state causes a branch to a subsequent state. PAUSE IR The input and output of instructions can be interrupted in this state. UPDATE IR The instruction is clocked into the second stage of the instruction register parallel to the falling edge of TCK in this state. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description Description 137 ...

Page 150

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator JTAG Boundary-Scan Specification Instruction Register The instruction register (IR bits in length. Table 63 shows the BS instructions implemented by the T7633. Table 63. T7633’s Boundary-Scan Instructions Instruction Code EXTEST 0000 IDCODE 0001 HIGHZ 0100 SAMPLE/PRELOAD 0101 BYPASS 1111 EVERYTHING ELSE — ...

Page 151

... The BYPASS register is a one-stage, shift register that enables the shift chain to be reduced to one stage in the T7633. IDCODE Register The IDCODE register identifies the T7633 by means of a parallel, loadable, 32-bit shift register. The code is loaded on the rising edge of TCK in the CAPTURE-DR state. The 32-bit data is organized into four sections as follows. Table 64. IDCODE Register ...

Page 152

... Microprocessor Interface Overview The T7633 device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. The microprocessor interface provides access to all the internal registers through a 12-bit address bus and an 8-bit data bus. Inputs MPMODE and MPMUX (pins 74 and 76) are used to configure this inter- face into one of four possible modes, as shown in Table 65 ...

Page 153

... MHz clock derived from the CHI clock. 2. The DTACK output is asynchronous to MPCLK. 3. MPCLK is needed if RDY output is required to be synchronous to MPCLK the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Generic Pin_Type Pin Name ...

Page 154

... REGBANK0 con- tains the global registers which are common to all the circuit blocks on T7633. REGBANK1 is reserved and must not be written. REGBANK[2, 5] are attached to the LIU circuit blocks. REGBANK[3, 6] are attached to the framer circuit blocks ...

Page 155

... Address Valid to AS Falling Edge t22 AS Falling Edge to Address Invalid t23 AS Falling Edge to DS Asserted (Read) t24 AS Falling Edge to DS Asserted (Write) t25 CS Asserted to DS Asserted (Write) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Parameter — Setup Hold Delay (ns) (ns) (ns) ...

Page 156

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Microprocessor Interface I/O Timing (continued) Table 69. Microprocessor Interface I/O Timing Specifications (continued) Symbol Configuration t31 Modes 3 & 4 ALE Asserted Width t32 Address Valid to ALE Deasserted t33 ALE Deasserted to Address Invalid t34 CS Asserted to RD Asserted t35 Address Valid and ALE Asserted to RD Asserted ...

Page 157

... DTACK AD[0:7] Figure 59. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = A[0:11] VALID ADDRESS t5 R/W DS DTACK AD[0:7] Figure 60. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued t10 t9 t3 t16 t20 t25 t8 t7 t17 VALID DATA t11 t12 ...

Page 158

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Microprocessor Interface I/O Timing (continued t21 t22 A[8:11] VALID ADDRESS t5 R/W DS t23 DTACK t21 t22 AD[0:7] VALID ADDRESS Figure 61. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = t21 t22 A[8:11] VALID ADDRESS t5 R/W DS t24 DTACK t21 t22 AD[0:7] VALID ADDRESS Figure 62. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) ...

Page 159

... AD[0:7] MPCK Figure 63. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) CS ALE A[0:11] VALID ADDRESS WR RDY AD[0:7] MPCK Figure 64. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) t33 t34 t50 t35 t37 t39 t38 t31 t32 t33 t44 t51 ...

Page 160

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Microprocessor Interface I/O Timing (continued) CS ALE t52 t53 A[8:11] VALID ADDRESS RD t54 RDY t52 t53 AD VALID ADDRESS MPCK Figure 65. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) CS ALE t52 t53 A[8:11] VALID ADDRESS WR t55 RDY t52 t53 VALID ADDRESS AD MPCK Figure 66. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) ...

Page 161

... Table 71. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations Greg4 Bit 4 Bit Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Status Register GREG0 LIU_REG0 FRM_SR0—FRM_SR7 FDL_SR0 INTERRUPT (Pin 99) Asserted Value Deasserted Value High High 3-state Low ...

Page 162

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Register Architecture Table overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 72. Register Summary Register GREG0 Primary Block Interrupt Status GREG1 Primary Block Interrupt Enable ...

Page 163

... NT1-RE Unavailable Seconds Counter FRM_SR51 FRM_SR52 Receive NOT-FAS TS0 FRM_SR53 Received Sa SLC -96 FDL/CEPT Sa Receive Stack FRM_SR54— FRM_SR63 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Function Register Address (hex) Channel 1 Channel 2 610, 611 C10, C11 612, 613 C12, C13 614, 615 ...

Page 164

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Register Architecture (continued) Table 72. Register Summary (continued) Register FRM_RSR0— Received Signaling FRM_RSR31 FRM_PR0— Interrupt Group Enable FRM_PR7 FRM_PR8 Framer Mode Option FRM_PR9 Framer CRC Control Option FRM_PR10 Alarm Filter FRM_PR11 Errored Second Threshold FRM_PR12, Severely Errored Second Threshold ...

Page 165

... FDL Transmitter Status FDL_SR2 FDL Receiver Status FDL ANSI Bit Codes Status FDL_SR3 FDL_SR4 FDL Receive FIFO Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Function Transmit Signaling Registers Facility Data Link Registers Register Address (hex) Channel 1 Channel 2 691—694 C91—C94 695— ...

Page 166

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Global Register Architecture REGBANK0 contains the status and programmable control registers for all global functions. The address of these registers is 000 (hex) to 008 (hex). These registers control both channels of the terminator. The register bank architecture is shown in Table 73. The register bank consists of 8-bit registers classified as pri- mary block interrupt status register, primary block interrupt enable register, global loopback control register, global terminal control register, device identification register, and global internal interface control register ...

Page 167

... LIU2IE Line Interface 2 Interrupt Enable enables LIU2 interrupts. 5 FRMR2IE Framer 2 Interrupt Enable enables framer 2 interrupts. 6 FDL2IE Facility Data Link 2 Interrupt Enable enables FDL2 interrupts. 7 — Reserved. Write to 0. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Description Description 155 ...

Page 168

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Global Register Structure Global Loopback Control Register (GREG2) This register enables the framer inputs RCHIDATA1 and RCHIDATAB1 to be driven by various internal sources enables the specified loopback. The default of the register 00 (hex) disables all loopbacks and enables external sources to drive these inputs ...

Page 169

... GREG5 Device Code GREG6 Version # GREG7 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Description Description Programs the interrupt pin to be active-high (1 state) when there is an interrupt condition and to be inactive (0 state) when there is no interrupt condition. Programs the interrupt pin to be active-low (0 state) when there is an interrupt condition and to be inactive (1 state) when there is no interrupt condition ...

Page 170

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Unit (LIU) Register Architecture REGBANK2 and REGBANK5 contain the status and programmable registers for the line interface unit channels LIU1 and LIU2 respectively. The base address for REGBANK2 is 400(hex) and for REGBANK5 is A00(hex). Within these register banks the bit map is identical for both LIU1 and LIU2. ...

Page 171

... Enable Transmit Driver Monitor Interrupt enables an interrupt in response to 2 TDMIE TDM alarm. Enable loss of Transmit Clock Interrupt enables an interrupt in response to 3 LOTCIE LOTC alarm. 4—7 — Reserved. Write to 0. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator Description Description 159 ...

Page 172

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Control Registers The bits in the control registers allow the user to configure the various device functions for the individual line inter- face channels 1 and 2. All the control bits (with the exception of LOSSTD) are active-high. LIU Control Register (LIU_REG2) Table 83 ...

Page 173

... ALOS 1 0 DLOS 0 1 ALOS 0 1 DLOS 1 1 ALOS 1 1 DLOS Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Description RPD/RND 0 Normal Data 0 0 AIS (all ones) AIS (all ones RLCK Free Runs Recovered Clock Free Runs Free Runs Free Runs ...

Page 174

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Line Interface Control Registers LIU Control Register (LIU_REG4) Table 85. LIU Register (LIU_REG4) (404, A04) Bit Symbol 0 ALTIMER The ALTIMER bit is used to select the time required to declare ALOS. ALTIMER = 0 selects 1 ms—2.6 ms. ALTIMER = 1 selects 10 bit to 255 bit periods. ...

Page 175

... Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same trans- former as in CEPT 120 applications (see Line Interface Unit: Line Circuitry section). Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Description Short-Haul Applications ...

Page 176

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture REGBANK3 and REGBANK6 contain the status and programmable control registers for the framer and system (CHI) interface channels FRM1 and FRM2. The base address for REGBANK3 is 600 (hex) and for REGBANK6 is C00 (hex). Within these register banks, the bit map is identical for both FRM1 and FRM2. ...

Page 177

... Reserved. 7 S96SR SLC -96 Stack Ready indicates that either the transmit framer SLC -96 stack is ready for more data or the receive framer SLC -96 stack contains new data. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) Description 165 ...

Page 178

... Loss of Time Slot 16 Signaling Multiframe Alignment indicates the receive framer loss of time slot 16 signaling multiframe alignment in the CEPT mode. A search for a new time slot 16 signaling multiframe alignment starts once frame alignment is established. This bit is 0 when the T7633 is programmed for the transparent signaling mode, register FRM_PR44 bit 0 (TSIG LTSFA, Loss of Transmit Superframe Alignment ...

Page 179

... Received Sa6 = indicates the receive framer detected a Sa6 code equal to 1110. This bit the DS1 mode. 7 Sa6=F Received Sa6 = indicates the receive framer detected a Sa6 code equal to 1111. This bit the DS1 mode. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description 167 ...

Page 180

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers Facility Errored Event Register (FRM_SR3) A bit set to 1 indicates the receive framer has recently received the given errored event. Table 92. Facility Errored Event Register-1 (FRM_SR3) (603; C03) Bit Symbol 0 LFV Line Format Violation indicates the receive framer detected a bipolar line coding or excessive zeros violation ...

Page 181

... CMA New CEPT CRC-4 Multiframe Alignment indicates the CEPT CRC-4 multiframe alignment in the receive framer has been established. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description 169 ...

Page 182

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers Table 93. Facility Event Register-2 (FRM_SR4) (604; C04) (continued) Bit Symbol 4 FDL-PLBON, ESF FDL Payload Loopback On Code Detect indicates the receive framer detected the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the MSB ...

Page 183

... Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description 171 ...

Page 184

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers The following status registers are dedicated to the NT1 and the NT1 remote end (NT1-RE) interface. The alarm conditions to evaluate errored seconds and severely errored seconds are defined in Table 44, Event Counters Definition on page 97 and the NT1 and NT1-RE enable registers, FRM_PR16—FRM_PR18. The thresholds are defined in registers FRM_PR11— ...

Page 185

... Table 98. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) ((60A—60B); (C0A—C0B)) Register Byte Bit FRM_SR10 MSB 7—0 FRM_SR11 LSB 7—0 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description 15 – 1 pseudorandom pattern*. 20 – 1 quasi-random pattern*. Symbol BPV15—BPV8 BPVs Counter. ...

Page 186

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers CRC Error Counter Register (FRM_SR12—FRM_SR13) This register contains the 16-bit count of CRC errors. CRC errors are not counted during loss of CRC multiframe alignment. Table 99. CRC Error Counter Registers (FRM_SR12—FRM_SR13) ((60C—60D); (C0C—C0D)) ...

Page 187

... Byte Bit FRM_SR32 MSB 7—0 ETRESES15—ETRESES8 ET-RE Severely Errored Seconds Counter. FRM_SR33 LSB 7—0 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Symbol ETES15—ETES8 ET Errored Seconds Counter. ETES7—ETES0 ET Errored Seconds Counter. Symbol ETBES15—ETBES8 ET Bursty Errored Seconds Counter. ...

Page 188

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers Table 110. ET-RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23)) Register Byte Bit FRM_SR34 MSB 7—0 FRM_SR35 LSB 7—0 Table 111. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25)) ...

Page 189

... Table 120. Receive Sa Register (FRM_SR53) (635; C35) Bit 7 Bit 6 Bit Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Symbol NTREBES7—NTREBES0 NT1-RE Bursty Errored Seconds Counter. Symbol NTRESES7—NTRESES0 NT1-RE Severely Errored Seconds Counter. Symbol NTREUS15—NTREUS8 NT1-RE Unavailable Seconds Counter Bits. NTREUS7— ...

Page 190

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Status/Counter Registers SLC- 96 FDL/CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) In the SLC -96 frame format, FRM_SR54 through FRM_SR58 contain the received SLC -96 facility data link data block. When the framer loss of frame alignment or loss of signaling superframe alignment, these registers are not updated ...

Page 191

... Bit 7 FRM_RSR0: IRSM Mode Only FRM_RSR1—FRM_RSR15 FRM_RSR16: IRSM Only FRM_RSR[17:31] 1.This bit contains the IRSM information in time slot 0. In PCS0 or PCS1 signaling mode, this bit is undefined. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) TSPRM B5 TSPRM B4 TSPRM ...

Page 192

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Parameter/Control Registers Registers FRM_PR0—FRM_PR70 define the mode configuration of each framer. All are read/write registers. These registers are initially set to a default value upon a hardware reset, which is indicated in the register defini- tion. Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) The bits in this register group enable the status registers FRM_SR0— ...

Page 193

... Receive Signaling Ready Interrupt Enable Bit enables interrupts when receive signaling buffers are ready (MOS or CCS modes). 6 — Reserved. Write to 0. SLC -96 Interrupt Enable Bit enables interrupts when SLC -96 receive or transmit 7 SLCIE stacks are ready. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description 181 ...

Page 194

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Parameter/Control Registers Secondary Interrupt Enable Registers (FRM_PR1—FRM_PR7) A bit set registers FRM_PR1—FRM_PR7 enables the generation of interrupts whenever the corresponding bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex). ...

Page 195

... Line Code Format Bit 7 LC2 B8ZS (T/R) 0 ZCS (T/R) 0 HDB3 (T/R) 0 Single Rail (DEFAULT) 1 AMI (T/R) 0 B8ZS (T), AMI (R) 1 ZCS (T), B8ZS (R) 1 AMI (T), B8ZS (R) 1 Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Bit 7 Bit 6 Bit 5 Bit 4 FMODE4 FMODE3 ...

Page 196

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Parameter/Control Registers Framer CRC Control Option Register (FRM_PR9) This register defines the CRC options for the framer. The default setting is 00 (hex). Table 137. CRC Option Bits Decoding (FRM_PR9) (669, C69) FRM_PR9 CRC Options ...

Page 197

... Bit 7, Bit 6, FRM_PR10 FRM_PR10 ESM1 ESM0 Other Combinations Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) Description Errored Second (ES) Bursty Errored Second Definition (BES) Definition Default values in Table 44, Event Counters Definition on page 97 when: BES = 0 Errored events > EST Reserved ...

Page 198

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Parameter/Control Registers Errored Second Threshold Register (FRM_PR11) This register defines the errored event threshold for an errored second (ES). A one-second interval with errors less than the ES threshold value will not be detected as an errored second. Programming 00 (hex) into this register dis- ables the errored second threshold monitor circuitry if register FRM_PR10 bit and bit ...

Page 199

... Register Bit 7 Bit 6 FRM_PR17 0 0 FRM_PR18 One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment. Agere Systems Inc. T7633 Dual T1/E1 3.3 V Short-Haul Terminator (continued) (continued) 1 (FRM_PR15) Bit 5 Bit 4 1 (FRM_PR16) Bit 5 Bit 4 Bit 3 ...

Page 200

... T7633 Dual T1/E1 3.3 V Short-Haul Terminator Framer Register Architecture Framer Parameter/Control Registers Automatic AIS to the System and Automatic Loopback Enable Register The default value of this register is 00 (hex). Table 146. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) Bit ...

Related keywords

T7633 datasheet
T7633 data sheet
T7633 pdf datasheet
T7633 component
T7633 part
T7633 distributor
T7633 RoHS
T7633 datasheet download