HD6437034F20 HITACHI, HD6437034F20 Datasheet
HD6437034F20
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HD6437034F20 Summary of contents
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... SuperH RISC engine SH7032 and SH7034 HD6417032, HD6477034, HD6437034 Name Hitachi Micro Systems, Incorporated 9/9/96 Hardware Manual ...
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... All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. ...
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... This Hardware Manual describes in detail the hardware functions of the SH7032 and SH7034. For information on the instructions, please refer to the Programming Manual. Related Manuals SH7000 Series Instructions "SH-1/SH-2 Programming Manual" (Document No. ADE-602-063B) For software development support tools, contact your Hitachi sales office Introduction ...
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Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the Sections within this manual. Table 1 Manual Organization Category Section Title Overview 1. Overview CPU 2. CPU Operating 3. Operating Modes ...
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Table 1 Manual Organization (cont) Category Section Title Pins 15. Pin Function Controller 16. Parallel I/O Ports Memory 17. ROM 18. RAM Power-Down 19. Power-Down States States Electrical 20. Electrical Char act Characteristics ...
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CPU 7. Clock pulse generator (CPG) Buses 8. Bus state controller (BC) 9. Direct memory access controller (DMAC) Memory 17. ROM 18. RAM 15. Pin function controller (PFC) 16. Parallel I/O ports Manual Organization Scheme 1. Overview 3. Operating ...
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Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas ...
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Section 1 Overview ............................................................................................ 1 1.1 SH Microcomputer Features.................................................................................................................... 1.2 Block Diagram............................................................................................................................................... 1.3 Pin Descriptions............................................................................................................................................. 1.3.1 Pin Arrangement........................................................................................................................... 1.3.2 Pin Functions.................................................................................................................................. 1.3.3 Pin Layout by Mode.................................................................................................................... 12 Section 2 CPU.................................................................................................... 15 2.1 Register Configuration................................................................................................................................ 15 2.1.1 General Registers (Rn).............................................................................................................. 15 ...
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Exception Process Vector Table........................................................................................... 52 4.2 Reset................................................................................................................................................................... 54 4.2.1 Reset Types .................................................................................................................................... 54 4.2.2 Power-On Reset ............................................................................................................................ 55 4.2.3 Manual Reset................................................................................................................................. 55 4.3 Address Errors................................................................................................................................................. 56 4.31 Address Error Sources................................................................................................................ 56 4.3.2 Address Error Exception Processing.................................................................................... 56 4.4 Interrupts ...
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Stack after Interrupt Exception Processing ...................................................................... 76 5.5 Interrupt Response Time............................................................................................................................ 77 Section 6 User Break Controller (UBC)............................................................. 79 6.1 Overview ........................................................................................................................................................... 79 6.1.1 Features............................................................................................................................................. 79 6.1.2 Block Diagram............................................................................................................................... 80 6.1.3 Register Configuration............................................................................................................... 81 6.2 Register Descriptions .................................................................................................................................. 82 ...
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Refresh Timer Counter (RTCNT) ........................................................................................ 116 8.2.9 Refresh Time Constant Register (RTCOR).................................................................... 117 8.2.10 Parity Control Register (PCR) .............................................................................................. 118 8.2.11 Notes on Register Access ........................................................................................................ 120 8.3 Address Space Subdivision...................................................................................................................... 121 8.3.1 Address Spaces and Areas....................................................................................................... 121 8.3.2 ...
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DMA Transfer Count Registers 0–3 (TCR0–TCR3).................................................... 177 9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ........................................ 177 9.2.5 DMA Operation Register (DMAOR) .................................................................................. 182 9.3 Operation........................................................................................................................................................... 184 9.3.1 DMA Transfer Flow..................................................................................................................... 184 9.3.2 DMA Transfer Requests............................................................................................................ 186 9.3.3 Channel Priority ...
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PWM Mode .................................................................................................................................... 262 10.4.5 Reset-Synchronized PWM Mode......................................................................................... 266 10.4.6 Complementary PWM Mode................................................................................................. 269 10.4.7 Phase Counting Mode................................................................................................................ 276 10.4.8 Buffer Mode.................................................................................................................................... 279 10.4.9 ITU Output Timing ...................................................................................................................... 285 10.5 Interrupts ........................................................................................................................................................... 286 10.5.1 Timing of Setting Status Flags.............................................................................................. ...
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Overview........................................................................................................................................... 322 11.3.2 Output Timing................................................................................................................................ 323 11.3.3 Examples of Use of Ordinary TPC Output........................................................................ 324 11.3.4 TPC Output Non-Overlap Operation.................................................................................... 327 11.3.5 TPC Output by Input Capture ................................................................................................. 331 11.4 Usage Notes..................................................................................................................................................... 332 11.4.1 Non-Overlap Operation.............................................................................................................. 332 Section 12 ...
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Serial Control Register.............................................................................................................. 355 13.2.7 Serial Status Register ................................................................................................................ 359 13.2.8 Bit Rate Register (BRR) ......................................................................................................... 363 13.3 Operation.......................................................................................................................................................... 371 13.3.1 Overview .......................................................................................................................................... 371 13.3.2 Operation in Asynchronous Mode ........................................................................................ 373 13.3.3 Multiprocessor Communication ............................................................................................ 384 13.3.4 Clocked Synchronous ...
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Overview ........................................................................................................................................................... 441 16.2 Port A.................................................................................................................................................................. 441 16.2.1 Register Configuration............................................................................................................... 441 16.2.2 Port A Data Register (PADR)................................................................................................ 442 16.3 Port B.................................................................................................................................................................. 443 16.3.1 Register Configuration............................................................................................................... 443 16.3.2 Port B Data Register (PBDR)................................................................................................ 444 16.4 Port C.................................................................................................................................................................. 445 16.4.1 Register ...
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Control Signal Timing............................................................................................................... 475 20.3.3 Bus Timing...................................................................................................................................... 478 20.3.4 DMAC Timing............................................................................................................................... 510 20.3.5 16-bit Integrated Timer Pulse Unit Timing...................................................................... 512 20.3.6 Programmable Timing Pattern Controller and I/O Port Timing............................. 513 20.3.7 Watchdog Timer Timing.......................................................................................................... 514 20.3.8 Serial Communications Interface ...
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A.2.30 Interrupt Priority Setting Register B (IPRB)................................................................... 562 A.2.31 Interrupt Priority Setting Register C (IPRC)................................................................... 563 A.2.32 Interrupt Priority Setting Register D (IPRD)................................................................... 564 A.2.33 Interrupt Priority Setting Register E (IPRE).................................................................... 565 A.2.34 Interrupt Control Register (ICR)........................................................................................... 566 A.2.35 Break ...
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A.2.71 Next Data Register A (NDRA) (when the output triggers of TPC output groups 0 and 1 are different).............. 607 A.2.72 Next Data Register B (NDRB) (when the output triggers of TPC output groups 2 and 3 are same).................... 608 ...
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... SH Microcomputer Features The SH microcomputer (SH7000 series new generation reduced instruction set computer (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which strikingly improves instruction execution speed ...
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... Table 1.1 Features of the SH7032 and SH7034 Microcomputers Feature Description CPU Original Hitachi architecture 32-bit internal data paths General-register machine: • Sixteen 32-bit general registers • Three 32-bit control registers • Four 32-bit system registers RISC-type instruction set: • Instruction length: 16-bit fixed length for improved code efficiency • ...
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... One-stage write buffer improves the system performance Data bus parity can be generated and checked Simplifies connection to ROM, SRAM, DRAM, and peripheral I/O RAS and CAS signals for DRAM are output Tp cycles can be generated to assure RAS precharge time Address multiplexing is supported internally, so DRAM can be connected directly HITACHI 3 ...
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... Power-on reset or manual reset can be selected as the internal reset Serial communication Asynchronous or clocked synchronous mode is selectable interface (SCI) Can transmit and receive simultaneously (full duplex) (2 channels) On-chip baud rate generator in each channel Multiprocessor communication function A/D converter Ten bits Can be externally triggered Variable reference voltage 4 HITACHI 4 channels) can be output 8 channels ...
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... Masked 5.0 V ROM 3.3 V SH7032 None 5.0 V 3.3 V Operating Frequency Model 2–20 MHz HD6477034F20 2–16.6 MHz HD6477034F16 2–12.5 MHz HD6477034VF12 2–20 MHz HD6437034F20 2–16.6 MHz HD6437034F16 2–12.5 MHz HD6437034VF12 2–20 MHz HD6417032F20 2–16.6 MHz HD6417032F16 2–12.5 MHz HD6417032VF12 Package 112-pin plastic QFP (FP-112) HITACHI 5 ...
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... Internal lower data bus (16 bits) Notes: 1. The SH7032 has RAM and no PROM or Masked ROM. The SH7034 has RAM and PROM or Masked ROM SH7032, SH7034 ( Masked ROM version ) HITACHI Port A PROM or 1 masked ROM* memory CPU access ...
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... CC 82 MD2 81 MD1 80 MD0 79 RES 78 WDTOVF NMI XTAL 73 EXTAL PA15/IRQ3/DREQ1 68 PA14/IRQ2/DACK1* 67 PA13/IRQ1/DREQ0/TCLKB 66 2 PA12/IRQ0/DACK0* 65 PA11/DPH/TIOCB1 64 PA10/DPL/TIOCA1 63 PA9/AH/IRQOUT/ADTRG 62 PA8/BREQ PA7/BACK 59 PA6/RD 58 PA5/WRH (LBS) 57 PA4/WRL (WR) : SH7034 ( PROM version ) PP HITACHI 7 2 /TCLKA ...
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... WDTOVF 78 BREQ 62 BACK 60 Note: Pin the SH7032, SH7034 (Masked ROM version) and V CC (PROM version). 8 HITACHI I/O Name and Function I Power: Connected to the power supply. Connect all V pins to the system power supply . The chip CC will not operate if any V I Ground: Connected to ground. Connect all V pins to the system ground ...
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... O Row address strobe: DRAM row-address strobe-timing signal. O Column address strobe high: DRAM column-address strobe-timing signal outputs low level to access the upper eight data bits. On-chip Bus Size ROM in Area 0 Disabled 8 bits 16 bits Enabled ) into W HITACHI 9 ...
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... TIOCB4 TOCXA4, 104, 105 TOCXB4 TCLKA– 66, 67, 104, TCLKD 105 10 HITACHI I/O Name and Function O Column address strobe low: DRAM column-address strobe-timing signal outputs low level to access the lower eight data bits. O Read: Indicates reading of data from an external device. ...
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... Analog ground: Power supply pin for analog circuits. Connect to the V I/O Port A: 16-bit input/output pins. Input or output can be selected individually for each bit. I/O Port B: 16-bit input/output pins. Input or output can be selected individually for each bit. I Port C: 8-bit input pins. potential. CC potential. SS HITACHI 11 ...
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... SS 13 AD8 14 AD9 AD10 17 AD11 18 AD12 19 AD13 20 AD14 21 AD15 (HBS HITACHI PROM Mode (SH7034PR- Pin OM version) No. MCU Mode A10 D3 35 A11 D4 36 A12 D5 ...
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... PB9/TP9/TxD0 CC V 109 PB10/TP10/RxD1 CC V 110 PB11/TP11/TxD1 CC V 111 PB12/TP12/IRQ4/SCK0 112 PB13/TP13/IRQ5/SCK1 NC CC PROM Mode (SH7034PR- OM version ref HITACHI 13 ...
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... R1 mode and indirect indexed GBR R2 addressing mode. In some instruc- R3 tions, R0 functions as a source register or a destination register R10 R11 R12 R13 R14 R15 functions as a stack pointer (SP) during exception processing. Figure 2.1 General Registers (Rn) HITACHI 15 ...
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... GBR 31 VBR 16 HITACHI SR: Status register bit: The MOVT, CMP, TAS, TST, BT, BF, SETT, and CLRT instructions use the T bit to indicate a true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, ...
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... Figure 2.3 System Registers Initial Value Undefined Value of the stack pointer in the vector address table Bits I0–I3 are 1111(H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table HITACHI 17 ...
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... The hardware stack area, which is referred to by the hardware stack pointer (SP, R15), uses only long word data starting from address 4n because this area stores the program counter and status register (figure 2.5). Address 2n Address 4n 18 HITACHI Long word Figure 2.4 Data Format in Registers Address Address m ...
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... Table 2.2 Sign Extension of Word Data CPU of SH7000 Series MOV.W @(disp,PC),R1 ADD R1,R0 ........... .DATA.W H'1234 Note: The address of the immediate data is accessed by @(disp, PC). Description Data is sign-extended to 32 bits, and R1 becomes H'00001234 next operated upon by an ADD instruction. Conventional CPUs ADD.W #H'1234,R0 HITACHI 19 ...
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... Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or long word immediate data is not located in instruction codes but is stored in a memory table. The memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. 20 HITACHI Description Executes an ADD before branching to TRGET. ...
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... Accessing by Displacement Classification CPU of SH7000 Series 16-bit displacement MOV.W MOV.W ......... .DATA.W H'1234 Note: The address of the immediate data is accessed by @(disp, PC). #H'12,R0 @(disp,PC),R0 @(disp,PC),R0 @(disp,PC),R1 @R1,R0 H'12345678 @(disp,PC),R0 @(R0,R1),R2 Conventional CPU MOV.B #H'12,R0 MOV.W #H'1234,R0 MOV.L #H'12345678, R0 Conventional CPU MOV.B @H'12345678,R0 Conventional CPU MOV.W@(H'1234,R1),R2 HITACHI 21 ...
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... Pre-decre- @–Rn ment indirect register addressing 22 HITACHI Effective Addresses Calculation The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the content of register Rn. Rn The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed ...
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... GBR disp + (zero-extended) 1/2/4 The effective address is the GBR value plus the R0. GBR + R0 Equation Byte disp Word disp Long word disp Rn + disp 1/2 Byte: GBR + disp Word: GBR + disp Long word: GBR + disp 4 GBR + disp 1/2/4 GBR + R0 GBR + R0 HITACHI ...
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... PC relative disp:8 addressing disp:12 24 HITACHI Effective Addresses Calculation The effective address is the PC value plus an 8-bit displacement (disp). disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a long word operation. For a long word operation, the lowest two bits of the PC are masked ...
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... Source Operand — 0 — 0 Control register or system register Control register or system register Equation — — — Destination Instruction Operand Example — NOP nnnn: Direct MOVT register nnnn: Direct STS register nnnn: Indirect pre- STC.L decrement register Rn HITACHI 25 Rn MACH,Rn SR,@- ...
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... Note: In MAC instructions, nnnn is the source register. 26 HITACHI Source Destination Operand Operand mmmm: Direct Control register or register system register 0 mmmm: Indirect Control register or post-increment system register register mmmm: Direct — ...
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... Immediate Indirect indexed GBR iiiiiiii: Immediate R0 (Direct register) AND 0 iiiiiiii: Immediate — iiiiiiii: Immediate nnnn: Direct register 0 Example MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn @(disp,GBR),R0 MOV.L R0,@(disp,GBR) @(disp,PC),R0 BF disp BRA disp MOV.L @(disp,PC),Rn AND.B #imm,@(R0,GBR) #imm,R0 TRAPA #imm ADD #imm,Rn HITACHI 27 ...
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... SUB SUBC SUBV Logic 6 AND operations NOT OR TAS 28 HITACHI Function Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry ...
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... Return from subroutine procedure T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception processing Number of Instructions 133 HITACHI 29 ...
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... Execution cycle T bit — Note: Scaling ( performed according to the instruction operand size. See "SH-1/SH-2 Programming Manual" for details. 30 HITACHI Explanation Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* mmmm: Source register ...
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... Rn (disp + Rn) 1 (disp 2 + Rn) 1 (disp 4 + Rn) 1 Sign Rm) Sign Rm (R0 + Rn) 1 (R0 + Rn) 1 HITACHI 31 T bit — — — — — — — — — — — — — — — — — — — — ...
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... R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 32 HITACHI Instruction Code Operation Rm 0000nnnnmmmm0110 (R0 + Rm) 0000nnnnmmmm1100 extension (R0 + Rm) 0000nnnnmmmm1101 extension (R0 + Rm) 0000nnnnmmmm1110 (disp + GBR) extension (disp ...
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... MSB MSB M/Q byte sign- 1 extended Rn T bit — — Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 — HITACHI 33 ...
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... SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: The normal minimum number of cycles (numbers in parenthesis represent the number of cycles when there is contension with preceding following instructions). 34 HITACHI Execution Operation Cycles A word sign- 1 extended Rn A byte zero- 1 extended Rn A word zero- ...
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... T 0010nnnnmmmm1010 11001010iiiiiiii R0 ^ imm (R0 + GBR) Execution Cycles HITACHI 35 T bit — — — — — — — Test result Test result Test result Test result — — — ...
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... BT label 10001001dddddddd BRA label 1010dddddddddddd BSR label 1011dddddddddddd JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 Note: The execution state is three cycles when program branches, and one cycle when program does not branch. 36 HITACHI Operation T Rn MSB LSB ...
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... GBR Rn VBR Rn Rn–4 Rn, SR (Rn) Rn–4 Rn, GBR (Rn) Rn–4 Rn, VBR (Rn) MACH Rn Execution Cycles T bit — 1 LSB 1 — 1 — 3 LSB 3 — 3 — 1 — 1 — 1 — 1 — 1 — 1 — 1 — 4 — — 1 — 1 — 1 — 2 — 2 — 2 — 1 — HITACHI 37 ...
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... Note: Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. When contention occurs between instruction fetches and data access When the destination register of the load instruction (memory register used by the next instruction are the same. 38 HITACHI Operation MACL Rn– ...
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... SHLL Rn SHLR Rn CMP/PZRn STS.L MACH, STS.L MACL, @–Rn @–Rn Fx: 0010 Fx: 0011–1111 MD: 10 MD: 11 STC VBR,Rn MOV.L RM, @(R0,Rn) CLRMAC RTE STS PR,Rn MOV.L @(R0,Rm),Rn MOV.L Rm,@Rn MOV.L Rm,@-Rn DIV0S Rm,Rn XOR Rm,Rn OR Rm,Rn MULU Rm,Rn MULS Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn SUBC Rm,Rn SUBV ADDC Rm,Rn ADDV SHAL Rn SHAR Rn STS.L PR, @–Rn HITACHI 39 Rm,Rn Rm,Rn ...
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... EXTU.B Rm,Rn 0111 Rn imm 1000 00MD Rn disp 1000 01MD Rm disp 1000 10MD imm/disp 1000 11MD imm/disp 1001 Rn disp 1010 disp 1011 disp 40 HITACHI Fx: 0000 Fx: 0001 MD: 00 MD: 01 STC.L STC.L| SR,@–Rn GBR,@–Rn ROTL Rn ROTR Rn CMP/PL Rn LDS.L LDS.L @Rm+,MACH @Rm+,MACL LDC.L LDC.L ...
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... GBR),R0 GBR),R0 TST AND #imm:8,R0 #imm:8,R0 TST.B AND.B #imm:8, #imm:8, @(R0,GBR) @(R0,GBR) MOV.L @(disp:8,PC),Rn MOV #imm:8,Rn Fx: 0010 Fx: 0011–1111 MD: 10 MD: 11 MOV.L R0,@ TRAPA #imm:8 (disp:8,GBR) MOV.L MOVA @(disp:8, @(disp:8, GBR),R0 PC),R0 XOR OR #imm:8,R0 #imm:8,R0 XOR.B OR.B #imm:8, #imm:8, @(R0,GBR) @(R0,GBR) HITACHI 41 ...
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... The CPU has five processing states: reset, exception processing, bus release, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception processing states, see section 4, Exception Processing. For details on the power-down states, see section 19, Power Down States. 42 HITACHI ...
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... Exception Exception processing processing source occurs ends Bus request cleared Program execution state SBY bit cleared for SLEEP instruction Manual reset state Reset states RES = 1, NMI = 0 NMI interrupt source occurs SBY bit set for SLEEP instruction Standby mode Power-down state HITACHI 43 ...
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... The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. This is described in more detail in section 2.5.1, Power- Down State. Bus Release State: In the bus release state, the CPU releases rights to the bus to the device that has requested them. 44 HITACHI ...
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... State On-chip CPU Peripheral Regi- CPU Modules sters Halt Run Held Halt Halt and Held initialize* I/O RAM Ports Canceling Held Held 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset Held Held or 1. NMI high-Z* 2. Power-on reset (select- 3. Manual reset able) HITACHI 45 ...
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... Mode PROM mode. In this mode, the EPROM can be programmed. For details, see section 17, ROM. Do not set to mode 7 unless the product is the SH7034 (PROM version). Pin Settings MD1 MD0 Mode Name 0 0 MCU mode MCU mode MCU mode PROM mode Bus Width of Area 0 8 bits 16 bits On-chip ROM — HITACHI 47 ...
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... Section 4 Exception Processing 4.1 Overview 4.1.1 Exception Processing Types and Priorities As figure 4.1 indicates, exception processing may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in the priority order shown. HITACHI 49 ...
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... The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. 2. The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE. Figure 4.1 Exception Source Types and Priority 50 HITACHI • Power-on reset • Manual reset • CPU address error • DMA address error • ...
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... Starts when undefined code is decoded at a position other than directly after a delayed branch instruction (a delay slot). Starts when undefined code or an instruction that rewrites the PC is decoded directly after a delayed branch instruction (in a delay slot). HITACHI 51 ...
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... In exception processing, the exception service routine start address is fetched from the exception vector table indicated by this vector table address. Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how to calculate vector table addresses. 52 HITACHI ...
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... H'00000034–H'00000037 to H'0000007C–H'0000007F H'00000080–H'00000083 to H'000000FC–H'000000FF H'00000100–H'00000103 H'00000104–H'00000107 H'00000108–H'0000010B H'0000010C–H'0000010F H'00000110–H'00000113 H'00000114–H'00000117 H'00000118–H'0000011B H'0000011C–H'0000011F H'00000120–H'00000123 to H'000003FC–H'000003FF HITACHI 53 ...
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... Table 4.4 Reset Types Transition Conditions Reset NMI Power-on Reset High Manual Reset Low 54 HITACHI Calculation of Vector table Addresses (Vector table address) = (vector table address offset) = (vector number) 4 (Vector table address) = VBR + (vector table address offset) = VBR + (vector number) RES CPU On-Chip Peripheral Module ...
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... While the NMI pin remains low, if the RES pin is held low for a certain time then driven high in the manual reset state, manual reset exception processing begins. The CPU carries out the same operations as for a power-on reset. to assure that the LSI is cyc A manual reset cyc HITACHI 55 ...
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... Fetches the exception service routine start address from the exception vector table for the address error that occurred and starts program execution from that address. The branch that occurs here is not a delayed branch. 56 HITACHI Operation Instruction fetch from even address Instruction fetch from odd address ...
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... The IRQ and on-chip peripheral module interrupt priority levels can be set in interrupt priority level registers A–E (IPRA–IPRE) as shown in table 4.7. Priority levels 0–15 can be set. See section 5.3.1, Interrupt Priority Level Registers A-E (IPRA–IPRE), for details. Number of Sources HITACHI 57 ...
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... I3–I0. The exception service routine start address for the accepted interrupt is fetched from the exception vector table and the program branches to that address and starts executing. For further information on interrupts, see section 5.4, Interrupt Operation. 58 HITACHI Priority Comments 16 ...
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... TRAPA instruction, branches to that address, and starts program execution. The branch is not a delayed branch. Comments — Delayed branch instructions are: JMP, JSR, BRA, BSR, RTS, RTE. Instructions that rewrite the PC are: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF and TRAPA — HITACHI 59 ...
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... The CPU follows the same procedure as for illegal slot exception processing, except that the program counter (PC) value pushed on the stack in general illegal instruction exception processing is the top address of the illegal instruction with the undefined code. 60 HITACHI ...
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... Exception processing is never inserted between them. 4.6.2 Immediately after Interrupt-Disabling Instructions Interrupts are not accepted when the instruction immediately following an interrupt-disabled instruction is decoded. Address errors are accepted, however. Exception Source Address Error Interrupt X X HITACHI 61 ...
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... TRAPA instruction SR General illegal Start add- SP instruc- ress of illegal tion instruction SR Note: Stack status is based on a bus width of 16 bits. 62 HITACHI Type Interrupt Upper 16 bits Lower 16 bits Upper 16 bits Lower 16 bits Illegal slot instruc- Upper 16 bits tion Lower 16 bits Upper 16 bits ...
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... In SR and PC stacking, four is subtracted from each of the SPs so the SP values are not multiples of four after stacking either. Since the address value output during stacking is the SP value, the address that produced the error is exactly what is output. In such cases, the stacked write data will be undefined. HITACHI 63 ...
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... The interrupt controller can notify external devices (via the IRQOUT pin) that an onchip interrupt has occured. In this way an external device can, for example, be informed if an on- chip interrupt occurs while the chip is operating in a bus-released mode and the bus has been requested. 5.1.2 Block Diagram Figure 5 block diagram of the interrupt controller. HITACHI 65 ...
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... UBC: User break controller DMAC: Direct memory access controller ITU: 16-bit integrated-timer pulse unit SCI: Serial communications interface PRT: Parity control unit of BSC A/D: A/D converter Figure 5.1 Block Diagram of the Interrupt Controller 66 HITACHI Priority decision logic IPR IPRA–IPRE Module bus interface WDT: Watchdog timer ...
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... Inputs maskable interrupt request signals IRQ7 IRQOUT O Outputs a signal indicating an interrupt source has occurred. 2 Abbr. R/W Address* IPRA R/W H'5FFFF84 IPRB R/W H'5FFFF86 IPRC R/W H'5FFFF88 IPRD R/W H'5FFFF8A IPRE R/W H'5FFFF8C ICR R/W H'5FFFF8E Initial Value Bus width H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16 16, 32 HITACHI 67 ...
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... Interrupt priority registers A and B (IPRA and IPRB) can select priority levels from 0–15 for each pin. IRQ interrupt exception processing sets the interrupt mask level bits (I3–I0) in the status register (SR) to the priority level value of the IRQ interrupt that was accepted. 68 HITACHI ...
Page 84
... Priority Within Module in table 5.3 and cannot be changed. A reset assigns priority level 0 to IRQ and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources, and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 5.3. HITACHI 69 ...
Page 85
... Reserved ITU0 IMIA0 0–15 (0) IMIB0 OVI0 Reserved ITU1 IMIA1 0–15 (0) IMIB1 OVI1 Reserved ITU2 IMIA2 0–15 (0) IMIB2 OVI2 Reserved 70 HITACHI Priority Vec- IPR (bit Within tor numbers) Module No. — — 11 — — 12 IPRA (15–12) — 64 IPRA (11–8) — 65 IPRA (7–4) — ...
Page 86
... Default Address Offset in Priority Vector table Order H'00000170–H'00000173 H'00000174–H'00000177 H'00000178–H'0000017B H'0000017C–H'0000017F H'00000180–H'00000183 H'00000184–H'00000187 H'00000188–H'0000018B H'0000018C–H'0000018F H' 000001D0–H' 000001D3 000003FC–H' 000003FF Low HITACHI 71 ...
Page 87
... DMAC1, or DMAC2 and DMAC3, or the parity control unit and the A/D converter, or the watchdog timer and DRAM refresh control unit), those two modules have the same priority. A reset initializes IPRA–IPRE to H'0000. They are not initialized by the standby mode. 72 HITACHI ...
Page 88
... Interrupt is requested on falling edge of NMI input (initial value) Interrupt is requested on rising edge of NMI input Description Interrupt is requested when IRQ input is low (initial value) Interrupt is requested on falling edge of IRQ input — — — — — — IRQ4S IRQ5S IRQ6S R/W R/W R/W HITACHI 73 8 NMIE 0 R/W 0 IRQ7S 0 R/W ...
Page 89
... The CPU accesses the exception vector table at the entry for the vector number of the accepted interrupt, reads the start address of the exception service routine, branches to that address, and starts executing the program there. This branch is not delayed. Note: The interrupts selected edge sensing are held pending. 74 HITACHI ...
Page 90
... CPU, however, the pin IRQOUT remains low. Figure 5.2 Flowchart of Interrupt Operation No Level 15 No Yes interrupt? Yes Yes level 14? No Yes Level 14 No interrupt? Level 1 Yes interrupt Yes level 13? No Yes level 0? No HITACHI 75 No ...
Page 91
... Bus width is 16 bits stores the top address of the next instruction (return instruction) after the executed instruction. 3. The value of SP must always be a multiple of four. Figure 5.3 Stack after Interrupt Exception Processing 76 HITACHI 2 Upper 16 bits PC Lower 16 bits SR Upper 16 bits Lower 16 bits ...
Page 92
... Notes The longest sequence is the interrupt or address error exception processing sequence m4 interrupt- masking instruction follows, however, the time may be longer. 0.50–0. MHz ( m4) 0.90– 0. MHz HITACHI 77 ...
Page 93
... Overrun fetch First instruction of interrupt service rountine F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory access) Figure 5.4 Pipeline Operation When IRQ Interrupt Is Accepted 78 HITACHI Interrupt acceptance IRQ When the interrupt response time is 11 cycles Instruction fetched from memory where program is stored ...
Page 94
... Operand size (long word access, word access, or byte access) • When break conditions are met, a user break interrupt is generated. A user-created user break interrupt exception routine can then be executed. • When a break is set to a CPU instruction fetch, the break occurs just before the fetched instruction. HITACHI 79 ...
Page 95
... Break condition comparator User break interrupt generating circuit UBC BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address mask registers H and L BBR: Break bus cycle register Figure 6.1 Block Diagram of the User Break Controller 80 HITACHI Bus interface BARH BARL Interrupt request Interrupt controller ...
Page 96
... Note: Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. Abbr. R/W Address* BARH R/W H'5FFFF90 BARL R/W H'5FFFF92 BAMRH R/W H'5FFFF94 BAMRL R/W H'5FFFF96 BBR R/W H'5FFFF98 Initial Value Bus width H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16, 32 H'0000 8, 16, 32 HITACHI 81 ...
Page 97
... BA15 Bit name: 0 Initial value: R/W R/W: Bit: 7 Bit name: BA7 Initial value: 0 R/W: R/W • BARL Bits 15–0 (break address 15–0 (BA15–BA0)): BA15–BA0 store the lower bit values (bits 15–0) of the address of the break condition. 82 HITACHI BA30 BA29 BA28 R/W R/W R ...
Page 98
... Break address bit BAn is not included in the break condition BAM27 BAM26 BAM25 R/W R/W R BAM19 BAM18 BAM17 R/W R/W R BAM11 BAM10 BAM9 R/W R/W R BAM3 BAM2 BAM1 R/W R/W R/W HITACHI 83 8 BAM24 0 R/W 0 BAM16 0 R/W 8 BAM8 0 R/W 0 BAM0 0 R/W ...
Page 99
... Bits 15–8 (reserved): These bits always read as 0. The write value should always be 0. • Bits 7 and 6 (CPU cycle/DMA cycle select (CD1 and CD0)): CD1 and CD0 select whether to break on CPU and/or DMA bus cycles. Bit 7: CD1 Bit 6: CD0 HITACHI — — — — ...
Page 100
... Break on both instruction fetch and data access cycles Description No break interrupt occurs (initial value) Break only on read cycles Break only on write cycles Break on both read and write cycles Description Operand size is not a break condition (initial value) Break on byte access Break on word access Break on long word access HITACHI 85 ...
Page 101
... I3–I0 to level 14 or lower. Section 5, Interrupt Controller, described the handling of priority levels in greater detail. 4. The INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives it, it starts user break interrupt exception processing. Section 5.4, Interrupt Operation, describes interrupt exception processing in more detail. 86 HITACHI ...
Page 102
... Internal address bits 31–0 CD1 CPU cycle DMA cycle ID1 Instruction fetch Data access RW1 RW0 Read cycle Write cycle SZ1 Byte size Word size Long word size Figure 6.2 Break Condition Logic BAMRH/BAMRL CD0 ID0 SZ0 32 User break interrupt HITACHI 87 ...
Page 103
... When data access (CPU/DMAC) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. 88 HITACHI ...
Page 104
... A user break interrupt occurs when long word data is read from address H'0076BCDC. • Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094 Conditions set: Address = H'002345C8, Bus cycle = DMA, instruction fetch, read (operand size not included) No user break interrupt occurs, because a DMA cycle includes no instruction fetch. HITACHI 89 ...
Page 105
... When the next instruction or the one after that is set as a break condition, a branch will result in the generation of a user break interrupt at the next instruction or the instruction after that, neither of which instructions will be executed. 90 HITACHI Next-instruction overrun fetch Branch destination fetch Next-instruction overrun fetch ...
Page 106
... The clock pulse produced by the crystal resonator and internal pulse generator is sent to the duty cycle correction circuit where its duty cycle is corrected then supplied to the LSI and to external devices. Duty correcting Oscillator circuit CPG Internal clock ( ) and HITACHI 91 ...
Page 107
... Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 7.2. XTAL Figure 7.3 Crystal Resonator Equivalent Circuit Table 7.2 Crystal Resonator Parameters Parameter 2 Rs max [ ] 500 Co max [pF] 7 Value to be determined (TBD) 92 HITACHI EXTAL =10–22 pF XTAL 4 8 500 200 ...
Page 108
... V cc VIL t EXr Table 7.3 Input Clock Specifications 5 V Specifications (fmax = 20 MHz –V ) Max = 5 EXr (1/2 V Min = 10 EXH/L CC standard) Open t cyc t t EXH EXL VIH t EXf Figure 7.5 Input Clock Waveform 3.3 V Specifications (fmax = 12.5 MHz) Max = 10 Min = 20 XTAL EXTAL Units ns ns HITACHI 93 ...
Page 109
... MHz. Duty cycles may not be corrected if under 5 MHz, but AC characteristics for the high-level pulse width (t ) and low-level pulse width (t CH operate normally. Figure 7.7 shows the standard characteristics of a duty cycle correction. This duty cycle correction circuit is not for correcting the input clock's transient fluctuations and jutters. 94 HITACHI No crossing signal lines ...
Page 110
... Input duty Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics Input frequency 20 (MHz) HITACHI 95 ...
Page 111
... Supports parity check and generation for data bus Odd parity/even parity selectable Interrupt request generated for parity error (PEI interrupt request signal) • Refresh counter can be used as an 8-bit interval timer Interrupt request generated at compare match (CMI interrupt request signal) HITACHI 97 ...
Page 112
... CMI interrupt request DPH, DPL PEI interrupt request Interrupt controller WCR: Wait state control register BCR: Bus control register DCR: DRAM area control register RCR: Refresh control register 98 HITACHI Wait control unit Area control unit DRAM control unit Comparator Parity control ...
Page 113
... Column address strobe signal for accessing the lower 8 bits of the DRAM O Signal for holding the address for address/data multiplexing I Wait state request signal O Address output I/O Data I/O. During address/data multiplexing, address output and data input/output. I/O Parity data I/O for upper byte I/O Parity data I/O for lower byte HITACHI 99 ...
Page 114
... Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write only with word transfer instructions. See section 8.2.11, Register Access, for details on writing. 100 HITACHI Abbr. R/W Initial Value ...
Page 115
... On-chip peripheral module space in area 5: 8 bits when the A8 address bit bits when • Area 6: If A27 = 0, area bits when the A14 address bit bits when A14 is 1 • On-chip RAM space in area 7: Always 32 bits See table 8.6 in section 8.3, Address Space Subdivision, for more information on how the space is divided. HITACHI 101 ...
Page 116
... Bit 14 (multiplexed I/O enable bit (IOE)): IOE selects whether area 6 is used as external memory space or an address/data multiplexed I/O area. 0 sets it for external memory space and 1 sets it for address/data multiplexed I/O space. With address/data multiplexed I/O space, address and data are multiplexed and input/output is from AD15–AD0. Bit 14: IOE 0 1 102 HITACHI IOE WARP RDDTY ...
Page 117
... Warp mode: External and internal accesses are simultaneously performed Description RD signal high-level duty cycle is 50 state (initial value) RD signal high-level duty cycle is 35 state Description WRH, WRL, and A0 enabled (initial value) LBS, WR, and HBS enabled HITACHI 103 ...
Page 118
... When RW1 is set to 1, the number of wait states selected in wait state insertion bits 1 and 0 (RLW0 and RLW1) for CAS-before-RAS (CBR) refresh of the refresh control register (RCR) are inserted during the CBR refresh cycle, regardless of the status of the WAIT signal. 104 HITACHI 14 13 ...
Page 119
... DRAM Space Column add- ress cycle: 1 state, fixed (short pitch) Column address cycle: 2 states + wait state from WAIT (long 2 pitch)* Internal space Multi- On-chip On-chip Plexed Peripheral ROM and I/O Module RAM 4 states 3 states, 1 state, + wait fixed fixed states from WAIT HITACHI 105 ...
Page 120
... DMA single address mode transfer and whether wait states are used. WCR2 is initialized to H'FFFF by a power-on reset not initialized by a manual reset or by the standby mode. Bit: 15 Bit name: DRW7 Initial value: 1 R/W: R/W Bit: 7 Bit name: DWW7 Initial value: 1 R/W: R/W 106 HITACHI DRW6 DRW5 DRW4 R/W R/W R DWW6 DWW5 DWW4 ...
Page 121
... Areas 1, 3– states + wait states from WAIT Areas state + long wait state + Wait state from WAIT Multiplexed I/O Column address 4 states + cycle: 1 state, wait states from WAIT fixed (short pitch) Column address cycle: 2 states + wait state from WAIT (long pitch) HITACHI 107 ...
Page 122
... DMA memory write cycle* 1 Sampled during single-mode DMA memory write cycle (initial value) Note: Sampled in the address/data multiplexed I/O space. 108 HITACHI Single-mode DMA Memory Write Cycle States (External Memory Space) External Memory Space DRAM Space Areas 1, 3–5,7: 1 state, Column address ...
Page 123
... WAIT pin is not pulled up WAIT pin is pulled up (initial value) Description Inserts 1 state Inserts 2 states Inserts 3 states Inserts 4 states (initial value A6LW0 — — R/W — — — — — — — — HITACHI 109 8 — 0 — 0 — 0 — ...
Page 124
... WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When accessing an 8-bit space, only CASL and WRL signals are valid, regardless of CW2 settings. Bit 15L: CW2 0 1 110 HITACHI Description Inserts 1 state Inserts 2 states Inserts 3 states ...
Page 125
... Inserts 1-state precharge cycle (initial value) Inserts 2-state precharge cycle Description Normal mode: full access (initial value) Burst operation: high-speed page mode Description CAS signal high level duty cycle is 50% of the T CAS signal high level duty cycle is 35% of the T state (initial value) C state C HITACHI 111 ...
Page 126
... RFSHE RMODE Initial value: 0 R/W: R/W • Bit 15-8 (reserved): These bits always read as 0. 112 HITACHI Description Multiplex of row and column addresses disabled (initial value) Multiplex of row and column addresses enabled Row Address Bits Compared (in burst operation) (MXE = A8–A27 (initial value) A9– ...
Page 127
... Bits 3–0 (reserved): These bits always read as 0. The write value should always be 0. Description Refresh control disabled. RTCNT can be used as an 8-bit interval timer. (initial value) Refresh control enabled Description CAS-before-RAS refresh (initial value) Self-refresh Description Inserts 1 state (initial value) Inserts 2 states Inserts 3 states Inserts 4 states HITACHI 113 ...
Page 128
... RTCNT and RTCOR match. Bit 7: CMF Description 0 RTCNT does not equal the value of RTCOR (initial value) Cleared by reading CMF after it has been set to 1, then writing 0 in CMF 1 Value RTCNT is equal to the value of RTCOR 114 HITACHI — — — 0 ...
Page 129
... Bits 2–0 (reserved): These bits always read as 0. The write value should always be 0. Description Compare match interrupt request (CMI) is disabled (initial value) Compare match interrupt request (CMI) is enabled Bit 3: CKS0 Description 0 Clock input disabled (initial value /32 0 /128 1 /512 0 /2048 1 /4096 HITACHI 115 ...
Page 130
... A word transfer operation is used, H'69 is written in the top byte and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access. Bit: 15 Bit name: — Initial value: 0 R/W: — Bit: 7 Bit name: Initial value: 0 R/W: R/W 116 HITACHI — — — — — — ...
Page 131
... For details, see section 8.2.11, Notes on Register Access. Bit: 15 Bit name: — Initial value: 0 R/W: — Bit: 7 Bit name: Initial value: 1 R/W: R — — — — — — R/W R/W R — — — — — — R/W R/W R/W HITACHI 117 8 — 0 — R/W ...
Page 132
... When cleared to 0, there is no forced output; when set produces a forced output of high level from the DPH and DPL pins when data is output, regardless of the parity. Bit 14: PFRC Description 0 Parity output not forced (initial value) 1 High output forced 118 HITACHI PFRC PEO PCHK1 PCHK0 0 0 ...
Page 133
... Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0. Description Even parity (initial value) Odd parity Description Parity not checked and not generated (initial value) Parity checked and generated only in DRAM area Parity checked and generated in DRAM area and area 2 Reserved HITACHI 119 ...
Page 134
... Figure 8.2 Writing to RCR, RTCSR, RTCNT, and RTCOR Reading from RCR, RTCSR, RTCNT, and RTCORP: These registers are read like other registers. They can be read by byte and word transfer instructions. If read by word transfer, the value of the upper eight bits is H'00. 120 HITACHI ...
Page 135
... DRAM space (area 1); not output in other cases. When not output, becomes shadow. Area selection: Decoded to become chip select signals CS0–CS7 for areas 0–7 Figure 8.3 Address Format 4 Mbyte space Output address: Output from address pins A21–A0 HITACHI 121 A0 ...
Page 136
... For details, see the sections on the individual modules.) 6. Divided into 8-bit space and 16-bit space by value of address bit A14 7. Select with IOE bit of BCR 8. For SH7032 9. For SH7034 122 HITACHI Assign-able Capacity Memory (linear space) 1 ...
Page 137
... A27 bit is 0. Word (16-bit) data accessed from 8-bit bus areas and longword (32-bit) data accessed from 16-bit bus areas require two consecutive accesses. Longword (32-bit) data accessed from 8-bit bus areas requires four consecutive accesses. HITACHI 123 ...
Page 138
... The spaces of on-chip ROM (area 0), DRAM (area 1), on-chip peripheral modules (area 5) and on- chip RAM (area 7) have shadows of different sizes from those discussed above. See section 8.3.5, Description of Areas, for details. 124 HITACHI Area Selected Chip Select Pin Driven Low CS0 ...
Page 139
... Actual space accessed when addresses are specified Shadow (A23, A22 = 00) Shadow (A23, A22 = 01) Shadow (A23, A22 = 10) Shadow (A23, A22 = 11) 8-bit space by address by address by address by address 8-bit space Figure 8.4 Shadows Actual space Area accessible 4 Mbytes with A21–A0 Actual space Location actually accessed HITACHI 125 ...
Page 140
... When external memory space is accessed, the CS0 signal is valid. The external memory space has a long wait function, so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the areas 0 and 2 long wait insertion bits (A02LW1, A02LW0) of wait state controller 3 (WCR3). 126 HITACHI ...
Page 141
... H'0BFFFFF access, H'0C00000 001: 16-bit access Shadow • Valid addresses A21–A0 H'0FFFFFF (A23 and bit space bit space A22 not output) • CS0 valid • Long wait function MD2–MD0 = 000 or 001 HITACHI 127 space ...
Page 142
... H'1800000 Shadow H'9BFFFFF H'9C00000 H'1BFFFFF H'1C00000 Shadow H'9FFFFFF H'1FFFFFF A27 = 1: A27 = 0: 16-bit space 8-bit space DRAME = 0 or DRAME = 1, MXE = 0 128 HITACHI H'9000000 Actual space External memory space (4 Mbytes) • Valid address A21–A0 (A23 and A22 not output) • CS1 H'9FFFFFF valid Figure 8 ...
Page 143
... H'2FFFFFF 16-bit space Logical address space Shadow Shadow Shadow Shadow 8-bit space Figure 8.7 Memory Map of Area 2 Actual space External memory space (4 Mbytes) • Valid addresses A21–A0 (A23 and A22 not output) • CS2 valid • Long wait function HITACHI 129 ...
Page 144
... Shadow Shadow Shadow Shadow H'5FFFE00 Shadow H'5FFFFFF 8 or 16-bit space Note: Some registers in onchip peripheral modules can only be accessed as 8-bit registers even though they occupy 16 bits (see Appendix A). 130 HITACHI H'D000000 H'D3FFFFF H'D400000 Actual space H'D7FFFFF H'D800000 On chip peripheral module space ...
Page 145
... Long wait function Figure 8.9 Memory Map of Area 6 Logical address space Shadow Actual space Shadow External memory space (4 Mbytes) Shadow • Valid addresses A21–A0 (A23 and A22 not output) • CS6 valid Shadow • Long wait function 16-bit space HITACHI 131 ...
Page 146
... Logical address space H'7000000 Shadow H'73FFFFF H'7400000 Shadow H'77FFFFF H'7800000 Shadow H'7BFFFFF H'7C00000 Shadow H'7FFFFFF 8-bit space 132 HITACHI H'F000000 H'F000FFF (SH7034) H'F001FFF (SH7032) Actual space External memory space (4 Mbytes) • Valid addresses A21–A0 (A23 and A22 not output) • CS7 valid ...
Page 147
... For details, see section 8.4.2., Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external memory space access. CK A21–A0 CSn RD (Read) AD15–AD0 (Read) Figure 8.11 Basic Timing of External Memory Space Access (1-state read timing) T1 HITACHI 133 ...
Page 148
... High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit (RDDTY) of the BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state, enabling longer access times for external devices. Only set to 1 when the operating frequency is a minimum of 10 MHz. 134 HITACHI T1 When RDDTY = 0 ...
Page 149
... CPU Write Cycle and DMAC Dual Mode Write Corresponding Bits in Cycle (Cannot be WCR1 and WCR2 = 1 controlled by WCR1)* 2 cycles fixed + wait state from WAIT signal 1 + wait state from WAIT 1 cycle + long wait state* signal 2 HITACHI 135 ...
Page 150
... When a high level is detected, it shifts to the final long wait state. Figure 8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6. 136 HITACHI T1 Tw (wait state) ...
Page 151
... WCR1; only write 1. When area 1 is being used as external memory space, never write 0 to bit 1 (WW1); always write 1. Wait states set in WCR3 LW1 LW2 Wait state Wait from WAIT states set signal input in WCR3 LW3 HITACHI 137 ...
Page 152
... When making an access to an 8-bit space, use the A0/HBS pin as A0 irrespective of the BAS bit value ( use the WRL/WR pin as the WR pin, and avoid using the WRH/LBS pin. 138 HITACHI Upper byte access T1 ...
Page 153
... SH microprocessors without additional multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR's multiplex shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table 8.9 illustrates the relationship between MXC1/MXC0 bits and address multiplexing. HITACHI 139 ...
Page 154
... A17 A8 A16 A7 A15 A6 A14 A5 A13 A4 A12 A3 A11 A2 A10 Note: The MXC1=1, MX0=1 setting is reserved. Do not use it. 140 HITACHI Shift Amount 9 bits Output Output Column Row Address Address A21 A20 A19 A18 Undefined A17 Value A16 A15 A14 A23 A13 ...
Page 155
... Figure 8.16 depicts address multiplexing with an 8-bit shift. RAS = Low level Internal address Address pin CAS = Low level Internal address Address pin Figure 8.16 Address Multiplexing States (8-bit shift) A23 A21 A16 A15 Undefined output A23 A22 A21 A21 HITACHI 141 ...
Page 156
... DRAM access time can be lengthened. Only set to 1 when the operating frequency is a minimum of 10 MHz. CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 142 HITACHI Row address Figure 8.17 Short Pitch Access Timing T c Column address CDTY = 0 ...
Page 157
... CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.18 Long Pitch Access Timing Row address Column address HITACHI 143 ...
Page 158
... When a high level is detected, it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle. 144 HITACHI T 2 ...
Page 159
... WRL signals are output. When accessing 8-bit space, WRL and CASL are output regardless of the CW2 setting. Figure 8.21 shows the control timing of the upper byte write cycle (short pitch) in 16-bit space Row address Column address (wait state HITACHI 145 ...
Page 160
... CASL WRH WRL CK A21–A0 RAS CASH CASL WRH Byte control WRL Figure 8.21 Byte Access Control Timing for DRAM Access 146 HITACHI Row address (a) Dual CAS signals (CW2 = Row address High level fixed High level (b) Dual WE signals (CW2 = 1) ...
Page 161
... DCR when there is an access outside the DRAM space during burst operation. Column address 1 Row address 2 Data 1 (a) Full access (read cycle) Column Column Column address 1 address 2 address 3 Data 1 Data 2 (b) Burst operation (read cycle) Column address 2 Data 2 Column address 4 Data 3 Data 4 HITACHI 147 ...
Page 162
... This timing is shown in figure 8.24. Likewise, when a write cycle continues after the read cycle for the same row address, a silent cycle is produced for 1 cycle. This timing is shown in figure 8.25. The details of timing are discussed in section 20.3.3, Bus Timing. 148 HITACHI ...
Page 163
... Column Column address A-1 address A-2 Read data A-1 Read data A-2 Write data B-1 Write data B-2 the same row address) Access B Silent cycle Column Column address B-1 address B-2 Data B-1 Data B-2 Access B (write) Silent T T cycle c c Column Column address B-1 address B-2 HITACHI 149 ...
Page 164
... See section 20.3.3, Bus Timing, for more information about the timing. CK A21–AD0 RAS CAS WR Read AD15–AD0 WR Write AD15–AD0 Figure 8.26 Long Pitch High-Speed Page Mode (Read/Write Cycle) 150 HITACHI Column address 1 Row address 1 Data 1 state. C ...
Page 165
... RAS CAS WR AD15– AD0 External memory space access DRAM access Column Column address 1 address 2 Data 1 Data 2 Figure 8.27 RAS Down Mode DRAM access External Column Column memory address 3 address 4 Data 3 External memory data Data 4 HITACHI 151 ...
Page 166
... DRAM access is continuous. Figure 8.28 shows the timing when an external memory space access occurs during burst operation in the RAS up mode. DRAM access A21– A0 Row address RAS CAS AD15– AD0 152 HITACHI External memory space access Column Column External memory address 1 address 2 address Data 1 ...
Page 167
... RLW1 and RLW0 bits of the RCR will be inserted into the CBR refresh cycle, regardless of the status of the WAIT signal. Figure 8.29 shows the RTCNT operation and figure 8.30 shows the timing of the CBR refresh. For details on timing, see section 20.3.3, Bus Timing. HITACHI 153 ...
Page 168
... RTCOR RTCOR value H'00 Clock selected with CKS2–CKS0 Figure 8.29 Refresh Timer Counter (RTCNT) Operation CK RAS CAS Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal 154 HITACHI Compare match match with RTCOR CBR CBR CBR: CAS-before-RAS refresh Compare Compare ...
Page 169
... The LSI can be kept in the self-refresh state and shifted to standby mode by setting it to self- refresh mode, setting the standby bit (SBY) of the standby control register (SBYCR and then executing a SLEEP instruction RAS CAS Figure 8.31 Output Timing of Self-Refresh Signal Rcc HITACHI 155 ...
Page 170
... CKS2–CKS0 bits. After its use as an 8-bit interval timer, the RTCNT count value may be in excess of the set cycle. For this reason, write H'00 to the RTCNT to clear it before starting to use it again with new settings. RTCNT can then be restarted and an interrupt obtained after the correct interval. 156 HITACHI Type of Bus Cycle External Space Access DRAM Space ...
Page 171
... WCR settings. Figure 8.32 shows the timing when the address/data multiplexed I/O space is accessed. CK A21– Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space T1 T2 Address Address T3 T4 Data (input) Data (output) HITACHI 157 ...
Page 172
... The byte access control signals when the address/data multiplexed I/O space is being accessed are of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external memory space access. These types can be selected using the BAS bit of the BCR. See section 8.4.3, Byte Access Control, for details. 158 HITACHI Tw (wait state) T1 ...
Page 173
... The external write cycle and internal access cycle will be performed in parallel from the next state on, without waiting for the end of the external write cycle. Figure 8.34 shows the timing when an access to an on-chip peripheral module and an external write cycle are performed in parallel. HITACHI 159 ...
Page 174
... The WCR1–WCR3 registers of the BSC can be set to control sampling of the WAIT signal when accessing various areas and the number of bus cycle states. Table 8.11 shows the number of bus cycle states when accessing various areas. 160 HITACHI External space writing On-chip peripheral module read/write ...
Page 175
... Corresponding Bits in WCR1 and WCR2 = 1 WAIT signal 1 state + long wait state* + wait states from WAIT signal Column address cycle: 2 states + wait states from WAIT signal (long pitch) WW1 of WCR1=1 Column address cycle: 2 states + wait states from WAIT signal (long pitch) HITACHI 161 ...
Page 176
... BACK pin. Figure 8.35 illustrates the bus release procedure. SH microprocessor BREQ received Strobe pin: High-level output Address, data, strobe pin: High impedance Bus release response Bus released 162 HITACHI BREQ = low BACK = low Figure 8.35 Bus Release Procedure External device Bus request BACK acknowledge Bus acquisition ...
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... LSI (See figure 8.37). When a refresh request is generated and BACK returns to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where BACK was originally supposed to become low. BREQ BACK Figure 8.36 BACK Operation by Refresh Demand (1) Refresh damand Refresh execution HITACHI 163 ...
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... For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike above 2.0 V. Note that delay of the BACK signal increases approximately in units of 0.1 ns/pF. (When a capacitance of 220 pF is added, the delay increases approximately by 22 ns.) 164 HITACHI BACK = does not become low level. Pulse width of the spike is approx ns. ...
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... To capture the BACK signal using the flip-flop, receive the BACK signal using a single flip-flop then distribute the signal (see figure below). BACK BACK C SH7000 Trigger BACK Trigger HITACHI 165 ...
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... CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines). CK RES A0–A21 RAS CAS WR AD0–AD15 166 HITACHI long pitch/high-speed page mode Tp RES latch timing Manual reset Row address Figure 8.38 Long-pitch Mode Write (1) 1.5 tcyc), causing the ...
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... CAS WR AD0–AD15 CK RES A0–A21 RAS CAS RD Tp Manual reset Row address Figure 8.39 Long-pitch Mode Write (2) Tp RES latch timing Manual reset Row address Figure 8.40 Long-pitch Mode Read (1) Tr Tc1 Tc2 FFFF Data output Tr Tc1 Tc2 Colum address FFFF HITACHI 167 ...
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... RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the DRAM). The countermeasures are not required when DRAM data is initialized or loaded again after manual reset. 168 HITACHI Tp Manual reset Row address Figure 8.41 Long-pitch Mode Read (2) ) ...
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... WRH and WRL signals of this LSI and write with delayed writing. Normal data is also delay- written, causing no problems. RAS SH Micro- computer CAS RD WRH or WRL CK Notes: 1. For preventing signal racing 2. Negative edge latch Figure 8.42 Delayed-Write Control Circuit *1 *1 DWRH or DWRL Symbol Min t -5ns DS RAS CAS OE WE DRAM HITACHI 169 ...
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... External memory and on-chip memory Memory-mapped external devices and on-chip peripheral module (excluding the DMAC itself) External memory and on-chip memory Memory-mapped external device and on-chip peripheral module (excluding the DMAC) Two on-chip memories On-chip memory and on-chip peripheral modules (excluding DMAC) HITACHI 171 ...
Page 185
... Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes • CPU can be asked for interrupt when data transfer ends • Maximum transfer rate 20 M words/s (320 MB/s) For 5 V and 20 MHz Bus mode: Burst mode Transmit size: Word 9.1.2 Block Diagram Figure 9 block diagram of the DMAC. 172 HITACHI ...
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... TCRn: DMA transfer count register CHCRn: DMA channel control register DEIn: DMA transfer-end interrupt request to CPU. n: 0–3 Iteration control Register control Start-up control Request priority control Bus interface Bus controller Figure 9.1 DMAC Block Diagram SARn DARn TCRn CHCRn DMAOR DMAC HITACHI 173 ...
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... Pin Configuration Channel Name 0 DMA transfer request DMA transfer request acknowledge 1 DMA transfer request DMA transfer request acknowledge 174 HITACHI Symbol I/O Function DREQ0 I DMA transfer request input from external device to channel 0 DACK0 O DMA transfer request acknowledge output from channel 0 to external ...
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... DMAOR R/(W)* H'0000 Access Address Size H'5FFFF40 16, 32 H'5FFFF44 16, 32 H'5FFFF4A 16, 32 H'5FFFF4E 8, 16, 32 H'5FFFF50 16, 32 H'5FFFF54 16, 32 H'5FFFF5A 16, 32 H'5FFFF5E 8, 16, 32 H'5FFFF60 16, 32 H'5FFFF64 16, 32 H'5FFFF6A 16, 32 H'5FFFF6E 8, 16, 32 H'5FFFF70 16, 32 H'5FFFF74 16, 32 H'5FFFF7A 16, 32 H'5FFFF7E 8, 16, 32 H'5FFFF48 8, 16, 32 HITACHI 175 ...
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... DAR is ignored in transfers from memory- mapped external devices or external memory to external devices with DACK). The initial value after resets or in standby mode is undefined. Bit: 31 Bit name: Initial value: — R/W: R/W Bit: 23 Bit name: Initial value: — R/W: R/W 176 HITACHI — — — R/W R/W R — — — R/W ...
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... R/W R/W R — — — R/W R/W R DM0 SM1 SM0 R/W R/W R R/(W) R/(W) R — — — R/W R/W R — — — R/W R/W R RS3 RS2 RS1 R/W R/W R R/W R/W R/(W)* HITACHI 177 8 — R/W 0 — R/W 8 RS0 0 R R/W ...
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... Bits 11–8 (resource select bits 3–0 (RS3–RS0)): RS3–RS0 specify which transfer requests will be sent to the DMAC. Do not change the transfer request source unless the DMA enable bit (DE The RS3–RS0 bits are initialized to 0000 by resets or in standby mode. 178 HITACHI Description Fixed destination address (initial value) ...
Page 192
... IMIA2 (On-chip ITU2 input capture/compare-match A interrupt 4 transfer request)* IMIA3 (On-chip ITU3 input capture/compare-match A interrupt 4 transfer request)* Auto-request (Transfer requests automatically generated 4 within DMAC)* ADI (A/D conversion end interrupt request of on-chip A/D 4 converter)* Reserved (illegal setting) Reserved (illegal setting HITACHI 179 ...
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... When the source of the transfer request is an on- chip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes with the RS Bit. Bit 180 HITACHI Description DACK is output in read cycle (initial value) DACK is output in write cycle Description DACK is active high (initial value) ...
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... Bit Description Byte (8 bits) (initial value) Word (16 bits) Description Interrupt request disabled (initial value) Interrupt requeste enabled Description DMA has not ended or was aborted (initial value) Cleared by reading 1 from the TE bit and then writing 0. DMA has ended normally HITACHI 181 ...
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... Bits 15–10 (reserved): These bits always read 0. The write value should always be 0. • Bits 9 and 8 (priority mode bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 182 HITACHI Description DMA transfer disabled (initial value) ...
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... To clear the AE bit, read 1 from it and then write 0. Address error by DMAC Description No NMI interrupt (initial value) To clear the NMIF bit, read 1 from it and then write 0. NMI has occurred Description Disable DMA transfers on all channels (initial value) Enable DMA transfers on all channels HITACHI 183 ...
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... If the IE bit of the CHCR is set this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Figure 9 flowchart of this procedure. 184 HITACHI ...
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... DREQ = level detection in the burst mode (external request), or cycle steal mode. 2. DREQ = edge detection in the burst mode (external request), or auto request mode 3. in burst mode. Figure 9.2 DMA Transfer Flowchart No No transfer request mode, DREQ detection selection 3 * Does No NMIF = DME = 0? Yes Transfer aborted 2 * Bus mode, system No HITACHI 185 ...
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... A/D conversion end interrupt (ADI) of the A/D converter (table 9.4). When this mode is selected, if the DMA transfer is enabled ( DME = NMIF = 0), a transfer is performed upon the input of a transfer request signal. 186 HITACHI Address Mode Source ...
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... Bus Mode Source nation RDR0 Any* Cycle steal Any TDR0 Cycle steal RDR1 Any* Cycle steal Any* TDR1 Cycle steal Any* Any* Burst/Cycle steal Any* Any* Burst/Cycle steal Any* Any* Burst/Cycle steal Any* Any* Burst/Cycle steal ADDR Any Burst/Cycle steal HITACHI 187 ...