CY7C09269-12AC Cypress Semiconductor Corporation., CY7C09269-12AC Datasheet
CY7C09269-12AC
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CY7C09269-12AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 6 Flow-Through/Pipelined devices — 16K x 16/18 organization (CY7C09269/369) — 32K x 16/18 organization (CY7C09279/379) — 64K x 16/18 organization (CY7C09289/389) • 3 Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • ...
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... For CY7C09269 and CY7C09279, pin #18 connected IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-through device. 2 CY7C09269/79/89 CY7C09369/79/89 or LOW on CE for one clock cycle will power 0 1 LOW and CE ...
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... A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R [Note 8] 69 A14R [Note 9] 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 CNTRSTR 62 R/WR 61 GND 60 OER 59 FT/PIPER 58 I/O17R 57 GND 56 I/O16R 55 I/O15R 54 I/O14R 53 I/O13R 52 I/O12R 51 I/O11R CY7C09269/79/89 CY7C09269/79/89 CY7C09369/79/89 CY7C09369/79/ 215 195 35 30 0.05 0.05 ...
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... For read operations both Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >1100V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Industrial Shaded area contains advance information. 4 CY7C09269/79/89 CY7C09369/79/89 AND CE must be asserted –I/O 8/9L 15/17L Ambient Temperature + – ...
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... Test Conditions MHz 5. 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) ALLINPUTPULSES 3.0V 90% 90% 10% GND 3 ns AND CE must be asserted to their active states ( CY7C09269/79/89 CY7C09369/79/89 -9 -12 2.4 2.4 0.4 0.4 0.4 2.2 2.2 0.8 0.8 0.8 10 -10 10 –10 10 215 360 195 300 245 410 225 375 35 ...
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... CY7C09269/79/89 CY7C09369/79/89 CY7C09269/79/89 CY7C09369/79/ -12 Max Min Max Min Max ...
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... A A n+1 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09269/79/89 CY7C09369/79/ n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ ...
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... [19,20,21,22 MATCH HD t CD1 t CWDD VALID , R/W, CNTEN, and CNTRST = for the Left Port, which is being written to CY7C09269/79/89 CY7C09369/79/ CD2 CKHZ CKLZ CD2 CKHZ ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. PRELIMINARY [16,23,24,25 n+1 n CD2 CKHZ Q n READ NO OPERATION [16,23,24,25 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH 9 CY7C09269/79/89 CY7C09369/79/ n+3 n CD2 CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Q n+3 Q n+4 ...
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... n+1 n CD1 Q n CKHZ NO READ OPERATION [14,16,23,24 n OHZ READ WRITE 10 CY7C09269/79/89 CY7C09369/79/ n+2 n+3 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n+4 n+5 n CD1 Q n CKLZ DC READ t CD1 t CD1 ...
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... R/W and CNTRST = PRELIMINARY [26] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER [26 n+1 READ WITH COUNTER . IH 11 CY7C09269/79/89 CY7C09369/79/89 t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 COUNTER HOLD Q n+3 READ WITH COUNTER ...
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... UB, LB, and R and CNTRST = 28. The “Internal Address” is equal to the “External Address” when ADS = V PRELIMINARY A n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = CY7C09269/79/89 CY7C09369/79/89 [27,28 n+2 n n+3 n+4 WRITE WITH COUNTER . IH A n+4 ...
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... UB, and 30. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. PRELIMINARY WRITE READ ADDRESS 0 ADDRESS 0 13 CY7C09269/79/89 CY7C09369/79/ n READ READ ADDRESS 1 ...
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... Read OUT High-Z Outputs Disabled [31,35,36,37] CNTEN CNTRST I/O Mode Reset out( Load out( out( Increment out(n+ CY7C09269/79/89 CY7C09369/79/89 Operation Counter Reset to Address 0 Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09269-6AC 7.5 CY7C09269-7AC CY7C09269-7AI 9 CY7C09269-9AC CY7C09269-9AI 12 CY7C09269-12AC CY7C09269-12AI Shaded area contains advance information. 32K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09279-6AC 7.5 CY7C09279-7AC CY7C09279-7AI 9 CY7C09279-9AC CY7C09279-9AI 12 CY7C09279-12AC CY7C09279-12AI Shaded area contains advance information. ...
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... A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack 16 CY7C09269/79/89 CY7C09369/79/89 Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C09269/79/89 CY7C09369/79/89 51-85048-A ...