CY7C1470V25-200ACES Cypress Semiconductor Corporation., CY7C1470V25-200ACES Datasheet
CY7C1470V25-200ACES
Related parts for CY7C1470V25-200ACES
CY7C1470V25-200ACES Summary of contents
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... Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1470V25 and CY7C1472V25 available in lead-free 100 TQFP, and 165 fBGA packages. CY7C1474V25 available in 209-ball fBGA package. • Compatible with IEEE 1149.1 JTAG Boundary Scan • ...
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... DQs DQP DQP DQP DQP DQP DQP f DQP g DQP h INPUT E E REGISTER 0 CY7C1470V25-167 CY7C1472V25-167 CY7C1474V25-167 3.0 3.4 450 400 120 120 Page Unit ...
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... DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470V25 CY7C1472V25 CY7C1474V25 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... V b DDQ DDQ DDQ N DQP DDQ MODE A Document #: 38-05290 Rev. *E PRELIMINARY 165-Ball fBGA Pinout CY7C1470V25 (2M × 36 CEN CLK ...
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... TDI Pin Description controls DQ a and DQP , BW controls and DQP BW controls DQ and DQP CY7C1470V25 CY7C1472V25 CY7C1474V25 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb ...
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... The outputs are controlled DQP controlled DQP is controlled DQP is controlled CY7C1470V25 CY7C1472V25 CY7C1474V25 . During [71:0] is controlled DQP is controlled DQP is controlled left SS Page ...
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... LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables CY7C1470V25 CY7C1472V25 CY7C1474V25 /DQP for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 and DQ /DQP a,b,c,d a,b /DQP for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 & DQ /DQP ...
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... WE inputs are ignored and the burst counter is incremented. The correct BW (BW CY7C1474V25, BW for CY7C1470V25 and BW a,b,c,d CY7C1472V25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “ ...
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... Truth Table (continued) Operation Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Partial Write Cycle Description Function (CY7C1470V25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – ...
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... TAPs. The TAP operates using JEDEC-standard 2.5V or 1.8V I/O logic levels. The CY7C1470V25/CY7C1472V25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature ...
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... TAP controller’s capture set-up plus hold time (t plus portion of The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1470V25 CY7C1472V25 CY7C1474V25 Unlike the SAMPLE/PRELOAD Page ...
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... Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1470V25 CY7C1472V25 CY7C1474V25 TDOV t TDOX Min. Max ...
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... DDQ V = 1.8V DDQ V = 2.5V DDQ V = 1.8V DDQ GND ≤ V ≤ DDQ CY7C1472V25 CY7C1474V25 (2M x 36) (4M x 18) 000 000 01011 01011 001000 001000 100100 010100 00000110100 00000110100 00000110100 1 1 CY7C1470V25 CY7C1472V25 CY7C1474V25 DDQ 0.9V 50Ω 50Ω 20pF O Min. Max. 1.7 2.1 1.6 0.4 0.2 0.2 1 0 0.3 DD –0.3 0.7 –0.3 0.36 –5 5 ...
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... Description Boundary Scan Exit Order (x36) Bit # 165-Ball CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit Size (x72 – – 110 (continued P11 P10 R9 R10 R11 ...
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... CY7C1470V25 CY7C1472V25 CY7C1474V25 (continued) 165-Ball P11 P10 R9 R10 R11 M10 L10 K10 J10 H11 G11 F11 E11 D11 C11 ...
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... CY7C1470V25 CY7C1472V25 CY7C1474V25 (continued) 209-Ball W11 55 W10 56 V11 57 V10 58 U11 59 U10 60 T11 61 ...
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... Document #: 38-05290 Rev. *E PRELIMINARY (continued) 209-Ball ID A11 A10 CY7C1470V25 CY7C1472V25 CY7C1474V25 Page ...
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... V ≤ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1470V25 CY7C1472V25 CY7C1474V25 Ambient Temperature DDQ 0°C to +70°C 2.5V–5%/+5% 1. Min. Max. 2.375 2.625 2.375 ...
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... R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE R = 14KΩ 1.8V V DDQ OUTPUT 0 14KΩ INCLUDING JIG AND (b) SCOPE CY7C1470V25 CY7C1472V25 CY7C1474V25 TQFP 209-BGA 165-fBGA Max. Max. Max 165 fBGA ...
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... DDQ is the time power needs to be supplied above V is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1470V25 CY7C1472V25 CY7C1474V25 -200 -167 Min. Max. Min. Max 5.0 6.0 200 167 2.0 2.2 2.0 2.2 3.0 3.4 3.0 3.4 1.3 1 ...
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... CLZ D(A1) D(A2) D(A2+1) Q(A3) BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1470V25 CY7C1472V25 CY7C1474V25 DOH OEV CHZ Q(A4) Q(A4+1) D(A5) t OEHZ t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...
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... I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05290 Rev. *E PRELIMINARY D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE DDZZ High-Z DON’T CARE CY7C1470V25 CY7C1472V25 CY7C1474V25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI DESELECT or READ Only Page ...
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... CY7C1470V25-200AXC CY7C1472V25-200AXC CY7C1470V25-200BZC CY7C1472V25-200BZC CY7C1474V25-200BGC CY7C1470V25-200BZXC CY7C1472V25-200BZXC CY7C1474V25-200BGXC 167 CY7C1470V25-167AXC CY7C1472V25-167AXC CY7C1470V25-167BZC CY7C1472V25-167BZC CY7C1474V25-167BGC CY7C1470V25-167BZXC CY7C1472V25-167BZXC CY7C1474V25-167BGXC Shaded area contains advance information Please contact your local Cypress sales representative for availability of these parts. Lead-free BG packages (Ordering Code: BGX) will be available in 2005. ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05290 Rev. *E PRELIMINARY CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85050-*A Page ...
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... SEATING PLANE C Document #: 38-05290 Rev. *E PRELIMINARY 165-Ball FBGA ( 1.40 mm) BB165C CY7C1470V25 CY7C1472V25 CY7C1474V25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 209-Ball FBGA ( 1.76 mm) BB209A CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85167-** ...
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... Document History Page Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 Orig. of REV. ECN No. Issue Date Change ** 114677 08/06/02 *A 121519 01/27/03 *B 223721 See ECN *C 235012 See ECN *D 243572 See ECN *E 299511 See ECN Document #: 38-05290 Rev. *E ...