GVT71256G18T-5 Cypress Semiconductor Corporation., GVT71256G18T-5 Datasheet

GVT71256G18T-5

Manufacturer Part Number

GVT71256G18T-5

Description

256K x 18 Synchronous Pipelined Burst SRAM

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1327A-117AC.pdf (16 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

GVT71256G18T-5

Manufacturer:

GALVANTECH

Quantity:

20 000

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Features

Functional Description

The Cypress Synchronous Burst SRAM family employs high-

speed, low-power CMOS designs using advanced triple-layer

polysilicon, double-layer metal technology. Each memory cell

consists of four transistors and two high-valued resistors.

The

262,144x18 SRAM cells with advanced synchronous periph-

Selection Guide

Cypress Semiconductor Corporation

Document #: 38-05129 Rev. *A

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

• Fast access times: 3.5, 3.8, and 4.0 ns

• Fast clock speed: 166, 150, 133, and 117 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 3.5 ns and 3.8 ns

• Optimal for depth expansion (one cycle chip deselect

• 3.3V –5% and +10% power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

• Automatic power-down for portable applications

• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid

to eliminate bus contention)

pipeline

quence)

Array) and 100-pin TQFP packages

CY7C1327A/GVT71256G18

SSQ

at all inputs and outputs

256K x 18 Synchronous Pipelined Burst SRAM

SRAM

•

3901 North First Street

integrates

7C1327A-166

71256G18-3

425

3.5

eral circuitry and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a pos-

itive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (WEL, WEH, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual byte write allows individual byte to be written. WEL con-

trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and

DQP2. WEL and WEH can be active only with BWE being

LOW. GW being LOW causes all bytes to be written. Write

pass-through capability allows written data available at the

output for the immediately next Read cycle. This device also

incorporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

The CY7C1327A/GVT71256G18 operates from a +3.3V pow-

er supply and all outputs operate on a +2.5V supply. All inputs

and outputs are JEDEC standard JESD8-5 compatible. The

device is ideally suited for 486, Pentium®, 680x0, and Power-

PC™ systems and for systems that benefit from a wide syn-

chronous data bus.

7C1327A-150

71256G18-4

•

CY7C1327A/GVT71256G18

400

3.8

San Jose

CA 95134

7C1327A-133

71256G18-5

375

4.0

Revised November 13, 2002

•

7C1327A-117

71256G18-6

408-943-2600

350

4.0

Related parts for GVT71256G18T-5

GVT71256G18T-5 Summary of contents

Page 1

Features • Fast access times: 3.5, 3.8, and 4.0 ns • Fast clock speed: 166, 150, 133, and 117 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 3.5 ns and 3.8 ns • Optimal for ...

Page 2

Functional Block Diagram WEH# BWE# WEL# GW# CE# CE2 CE2# ZZ Power Down Logic OE# ADSP# A17-A2 ADSC# ADV# A1-A0 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, ...

Page 3

Pin Configurations CCQ V SSQ NC NC DQ9 DQ10 V SSQ V CCQ DQ11 DQ12 DQ13 DQ14 V CCQ V SSQ DQ15 DQ16 DQP2 NC V SSQ V CCQ NC ...

Page 4

Pin Configurations (continued CCQ DQ9 CCQ DQ12 J V CCQ DQ14 M V CCQ N DQ18 ...

Page 5

Pin Descriptions (continued) BGA Pins QFP Pins 7P, 6N, 6L, 7K, 58, 59, 62, 63, 6H, 7G, 6F, 7E, 68, 69, 72, ...

Page 6

Burst Address Table (MODE = NC/V First Second Third Address Address Address (external) (internal) (internal) A...A00 A...A01 A...A10 A...A01 A...A00 A...A11 A...A10 A...A11 A...A00 A...A11 A...A10 A...A01 [ Truth Table Address Operation Deselected Cycle, ...

Page 7

Partial Truth Table for Read/Write FUNCTION GW BWE READ H READ H WRITE one byte H WRITE all bytes H WRITE all bytes L Electrical Characteristics Over the Operating Range Parameter Description V Input High (Logic 1) Voltage IHD V ...

Page 8

Thermal Consideration Parameter Description Thermal Resistance - Junction to Ambient JA Thermal Resistance - Junction to Case JC Capacitance Parameter C Input Capacitance I C Input/Output Capacitance (DQ) O Typical Output Buffer Characteristics Output High Voltage Pull-up Current V (V) ...

Page 9

Switching Characteristics Over the Operating Range Parameter Description Clock t Clock Cycle Time KC t Clock HIGH Time KH t Clock LOW Time KL Output Times t Clock to Output Valid KQ t Clock to Output Invalid KQX t Clock ...

Page 10

Timing Diagrams [23] Read Timing CLK t S ADSP# ADSC ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note) ADV# OE# t KQLZ DQ Note: 23. CE active in this timing diagram means that all Chip ...

Page 11

Timing Diagrams (continued) [23] Write Timing CLK t S ADSP# ADSC ADDRESS WEL#, WEH#, BWE# GW# CE# (See Note) ADV# OE# t KQX DQ Q SINGLE WRITE Document #: 38-05129 Rev ...

Page 12

Timing Diagrams (continued) [23] Read/Write Timing CLK t S ADSP# ADSC ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note) ADV# OE# DQ Single Reads Document #: 38-05129 Rev Q(A1) ...

Page 13

... Ordering Information Speed (MHz) Ordering Code 166 CY7C1327A-166AC GVT71256G18T-3 CY7C1327A-166BGC GVT71256G18B-3 150 CY7C1327A-150AC GVT71256G18T-4 CY7C1327A-150BGC GVT71256G18B-4 133 CY7C1327A-133AC GVT71256G18T-5 CY7C1327A-133BGC GVT71256G18B-5 117 CY7C1327A-117AC GVT71256G18T-6 CY7C1327A-117BGC GVT71256G18B-6 Document #: 38-05129 Rev. *A CY7C1327A/GVT71256G18 Package Name Package Type A101 100-Lead Thin Quad Flat Pack BG119 119-Lead FBGA ( ...

Page 14

Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05129 Rev. *A CY7C1327A/GVT71256G18 51-85050-A Page ...

Page 15

Package Diagrams (continued) Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05129 Rev. *A ...

Page 16

Document History Page Document Title: CY7C1327A/GVT71256G18 256K x 18 Synchronous Pipelined Burst SRAM Document Number: 38-05129 Issue REV. ECN NO. Date ** 108984 09/25/01 *A 121072 11/13/02 Document #: 38-05129 Rev. *A Orig. of Change BRI New Cypress spec—converted from ...

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