MFC2000 Conexant Systems, Inc., MFC2000 Datasheet - Page 6

• Manufacturer Part Number: MFC2000
• Description: Multifunctional peripheral cjntroller 2000
• Manufacturer: Conexant Systems, Inc.

Figures
Figure 1-1. MFP System Diagram Using MFC2000 .............................................................................................................. 1-1
Figure 1-2: MFC2000 Function Diagram ............................................................................................................................... 1-4
Figure 2-1. MFC2000 Organization ....................................................................................................................................... 2-2
Figure 3-1. MFC2000 BGA Bottom View ............................................................................................................................. 3-10
Figure 4-1. MFC2000 Memory Map....................................................................................................................................... 4-6
Figure 4-2. MFC2000 Internal Memory Map.......................................................................................................................... 4-7
Figure 4-3. MFC2000 Cache Organization .......................................................................................................................... 4-19
Figure 4-4. 2-Way Interleave ROM Connection................................................................................................................... 4-26
Figure 4-5. Zero Wait State, Single Access, Normal Read, Normal Write ........................................................................... 4-36
Figure 4-6. One Wait State, Single Access, One Read, One Write ..................................................................................... 4-37
Figure 4-7. Two Wait States, Single Access, Read On Delayed (CS1n), Write Early Off (CS2n)........................................ 4-38
Figure 4-8. Zero Wait State, Burst Access, Normal Read, Normal Write............................................................................. 4-39
Figure 4-9. Fast Page Mode ROM Access 1,0,0 Read Access Followed by 1,1,1,1, Write Access.................................. 4-40
Figure 4-10. System Bus Timing Read/Write with Wait States ......................................................................................... 4-41
Figure 4-11. System Bus Timing Zero-Wait-State Read/Write.......................................................................................... 4-42
Figure 4-12. System Bus Timing 2-Way Interleave Read Timing (S = 1).......................................................................... 4-43
Figure 4-13. System Bus Timing 2-Way Interleave Write Timing (S = 0 or 1)................................................................... 4-44
Figure 4-14. External Interrupt Request Timing................................................................................................................... 4-54
Figure 4-15. DRAM Bank/Address Map............................................................................................................................... 4-56
Figure 4-16. Simplified DRAM Controller Block Diagram .................................................................................................... 4-59
Figure 4-17. DRAM Interface Example ................................................................................................................................ 4-60
Figure 4-18. 8-bit Memory Data Bus.................................................................................................................................... 4-65
Figure 4-19. 16-bit Memory Data Bus.................................................................................................................................. 4-65
Figure 4-20. CASn Non-Interleaved 8-bit DRAM Read........................................................................................................ 4-66
Figure 4-21. 2-Way Interleaved Memory with Halfword Bursts of Data ............................................................................... 4-66
Figure 4-22. 2-Way Interleaved DRAM Read (3 words) ...................................................................................................... 4-67
Figure 4-23. 2-Way Interleaved DRAM Write ...................................................................................................................... 4-67
Figure 4-24. Refresh Cycle.................................................................................................................................................. 4-68
Figure 4-25. DRAM Timing Read, Write and Wait States for Non-interleave Mode .......................................................... 4-68
Figure 4-26. DRAM Timing for 2-way Interleave Write ........................................................................................................ 4-69
Figure 4-27. DRAM Timing Read for 2-way interleave mode............................................................................................ 4-69
Figure 4-28. DRAM Refresh Timing .................................................................................................................................... 4-70
Figure 4-29. DRAM Battery Refresh Timing ........................................................................................................................ 4-70
Figure 4-30. Flash Control Block Diagram........................................................................................................................... 4-73
Figure 4-31. NAND-Type Flash Memory Access with Two Wait States .............................................................................. 4-75
Figure 4-32: External DMA Read Timing (Single Access, One Wait State) ......................................................................... 4-80
Figure 4-33. External DMA Write Timing (Single Access, One Wait State) ......................................................................... 4-81
Figure 4-34. USB Logical Channels Block Diagram ............................................................................................................ 4-82
Figure 5-1. Power Reset Block Diagram................................................................................................................................ 5-2
Conexant
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