HD6432393TE Renesas Electronics Corporation., HD6432393TE Datasheet
HD6432393TE
Related parts for HD6432393TE
HD6432393TE Summary of contents
Page 1
To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
Page 2
Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
Page 3
ADE-602-112B Rev. 3.0 3/11/03 Hitachi, Ltd H8S/2355 Series HD6432355, HD6472355 H8S/2353 HD6432353 H8S/2393 HD6432393 Hardware Manual ...
Page 4
Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
Page 5
The H8S/2355 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with ...
Page 6
Main Revisions and Additions in This Edition Page Section All 4 Table 1-1 Overview Product lineup 6 Figure 1-2 Block Diagram (H8S/2393 Figure 1-5 H8S/2393 Pin Arrangement (TFP-120: Top View) Figure 1-6 H8S/2393 Pin Arrangement (TFP-128: Top View) ...
Page 7
Page Section 570 Table 20-2 DC Characteristics (3) 574 Table 20-4 Clock Timing 576 Table 20-5 Control Signal Timing 578 Table 20-6 Bus Timing 586 Table 20-7 Timing of On-Chip Supporting Modules 591 Table 20-8 A/D Conversion Characteristics 592 Table ...
Page 8
Page Section 786 Figure C-2 (d) Port 2 Block Diagram (Pins P2 790 Figure C-4 (a) Port 4 Block Diagram 793 Figure C-5 (c) Port 5 Block Diagram (Pin P5 821, Appendix E Pin States at Power-On 822 824 Table ...
Page 9
Section 1 Overview ............................................................................................................ 1.1 Overview............................................................................................................................ 1.2 Block Diagram ................................................................................................................... 1.3 Pin Description................................................................................................................... 1.3.1 Pin Arrangement ................................................................................................... 1.3.2 Pin Functions in Each Operating Mode................................................................ 11 1.3.3 Pin Functions ........................................................................................................ 16 Section 2 CPU ..................................................................................................................... 23 2.1 Overview............................................................................................................................ 23 2.1.1 Features ...
Page 10
Basic Timing...................................................................................................................... 67 2.9.1 Overview............................................................................................................... 67 2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 67 2.9.3 On-Chip Supporting Module Access Timing ....................................................... 69 2.9.4 External Address Space Access Timing ............................................................... 70 Section 3 MCU Operating Modes 3.1 Overview............................................................................................................................ 71 3.1.1 Operating Mode ...
Page 11
Features ................................................................................................................. 95 5.1.2 Block Diagram...................................................................................................... 96 5.1.3 Pin Configuration.................................................................................................. 97 5.1.4 Register Configuration.......................................................................................... 97 5.2 Register Descriptions ......................................................................................................... 98 5.2.1 System Control Register (SYSCR)....................................................................... 98 5.2.2 Interrupt Priority Registers (IPRA to IPRK) ............................................ 99 5.2.3 ...
Page 12
Area Partitioning................................................................................................... 134 6.3.2 Bus Specifications ................................................................................................ 136 6.3.3 Memory Interfaces................................................................................................ 137 6.3.4 Advanced Mode.................................................................................................... 137 6.3.5 Areas in Normal Mode.......................................................................................... 138 6.3.6 Chip Select Signals ............................................................................................... 139 6.4 Basic Bus Interface ............................................................................................................ 140 6.4.1 Overview............................................................................................................... 140 6.4.2 Data ...
Page 13
DTC Transfer Count Register B (CRB)................................................................ 172 7.2.7 DTC Enable Registers (DTCER).......................................................................... 172 7.2.8 DTC Vector Register (DTVECR) ........................................................................ 173 7.2.9 Module Stop Control Register (MSTPCR)........................................................... 174 7.3 Operation............................................................................................................................ 175 7.3.1 Overview............................................................................................................... 175 7.3.2 Activation Sources................................................................................................ 177 7.3.3 DTC ...
Page 14
Overview............................................................................................................... 231 8.7.2 Register Configuration.......................................................................................... 232 8.7.3 Pin Functions ........................................................................................................ 234 8.8 Port A ................................................................................................................................. 236 8.8.1 Overview............................................................................................................... 236 8.8.2 Register Configuration.......................................................................................... 237 8.8.3 Pin Functions ........................................................................................................ 240 8.8.4 MOS Input Pull-Up Function................................................................................ 242 8.9 Port B ................................................................................................................................. 243 ...
Page 15
Register Descriptions ......................................................................................................... 284 9.2.1 Timer Control Register (TCR).............................................................................. 284 9.2.2 Timer Mode Register (TMDR)............................................................................. 289 9.2.3 Timer I/O Control Register (TIOR)...................................................................... 291 9.2.4 Timer Interrupt Enable Register (TIER)............................................................... 304 9.2.5 Timer Status Register (TSR) ................................................................................ 307 9.2.6 Timer ...
Page 16
Module Stop Control Register (MSTPCR)........................................................... 374 10.3 Operation............................................................................................................................ 375 10.3.1 TCNT Incrementation Timing.............................................................................. 375 10.3.2 Compare Match Timing........................................................................................ 376 10.3.3 Timing of External RESET on TCNT .................................................................. 378 10.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 378 10.3.5 Operation with ...
Page 17
Section 12 Serial Communication Interface (SCI) 12.1 Overview............................................................................................................................ 403 12.1.1 Features ................................................................................................................. 403 12.1.2 Block Diagram...................................................................................................... 405 12.1.3 Pin Configuration.................................................................................................. 406 12.1.4 Register Configuration.......................................................................................... 407 12.2 Register Descriptions ......................................................................................................... 408 12.2.1 Receive Shift Register (RSR) ............................................................................... 408 12.2.2 Receive Data ...
Page 18
Operation in GSM Mode ...................................................................................... 490 13.4 Usage Notes ....................................................................................................................... 491 Section 14 A/D Converter 14.1 Overview............................................................................................................................ 495 14.1.1 Features ................................................................................................................. 495 14.1.2 Block Diagram...................................................................................................... 496 14.1.3 Pin Configuration.................................................................................................. 497 14.1.4 Register Configuration.......................................................................................... 498 14.2 Register Descriptions ......................................................................................................... 499 ...
Page 19
Section 17 ROM .................................................................................................................... 529 17.1 Overview............................................................................................................................ 529 17.1.1 Block Diagram...................................................................................................... 529 17.1.2 Register Configuration.......................................................................................... 530 17.2 Register Descriptions ......................................................................................................... 530 17.2.1 Bus Control Register L (BCRL) ........................................................................... 530 17.3 Operation............................................................................................................................ 531 17.4 PROM Mode...................................................................................................................... 532 17.4.1 PROM Mode Setting ...
Page 20
Clearing Software Standby Mode......................................................................... 559 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ... 560 19.6.4 Software Standby Mode Application Example .................................................... 560 19.6.5 Usage Notes .......................................................................................................... 561 19.7 Hardware Standby Mode ................................................................................................... 562 19.7.1 Hardware Standby ...
Page 21
C.10 Port D Block Diagram........................................................................................................ 804 C.11 Port E Block Diagram........................................................................................................ 805 C.12 Port F Block Diagram ........................................................................................................ 806 C.13 Port G Block Diagram........................................................................................................ 814 Appendix D Pin States D.1 Port States in Each Mode ................................................................................................... 817 Appendix E Pin ...
Page 22
Overview The H8S/2355 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen ...
Page 23
Table 1-1 Overview Item Specification CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract : ...
Page 24
Item Specification 8-bit timer 8-bit up-counter (external event count capability) 2 channels Two time constant registers Two-channel connection possible Watchdog timer Watchdog timer or interval timer selectable Serial Asynchronous mode or synchronous mode selectable communication Multiprocessor communication function interface (SCI) ...
Page 25
Item Specification Operating Seven MCU operating modes modes CPU Operating Mode Mode 1 Normal Advanced Clock Built-in duty correction circuit pulse generator Packages 120-pin plastic TQFP (TFP-120) 128-pin plastic QFP (FP-128) Product 5 V ...
Page 26
Block Diagram Figure 1-1 and figure 1-2 show a internal block diagrams of the H8S/2355 and H8S/2353, and the H8S/2393 EXTAL XTAL STBY RES WDTOVF NMI PF /ø / ...
Page 27
EXTAL XTAL STBY RES WDTOVF NMI PF /ø / / /HWR 4 PF /LWR 3 PF /WAIT 2 PF /BACK 1 PF /BREQ 0 PG /CS0 4 PG ...
Page 28
Pin Description 1.3.1 Pin Arrangement Figures 1-3 and 1-4 show the pin arrangement of the H8S/2355 and H8S/2353, and figure 1-5 and 1-6 show the pin arrangement of the H8S/2393. P5 /SCK2 /ADTRG ...
Page 29
AV 103 CC V 104 ref P4 / AN0 105 AN1 106 AN2 107 AN3 108 AN4 109 AN5 110 5 P4 /AN6/ DA0 111 ...
Page 30
P5 / SCK2 /ADTRG ref 95 P4 /AN0 /AN1 /AN2 /AN3 /AN4 4 100 P4 /AN5 5 101 ...
Page 31
AV CC 104 V ref 105 P4 /AN0 0 106 P4 /AN1 1 107 P4 /AN2 2 108 P4 /AN3 3 109 P4 /AN4 4 110 P4 /AN5 5 111 P4 /AN6 6 112 P4 /AN7 7 113 AV ...
Page 32
Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2355 Series in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128 Mode ...
Page 33
Pin No. TFP-120 FP-128 Mode /IRQ7 /IRQ3 /IRQ2 P6 6 — — /IRQ1 ...
Page 34
Pin No. TFP-120 FP-128 Mode /RxD1 /SCK0 /SCK1 — — ...
Page 35
Pin No. TFP-120 FP-128 Mode 1 STBY XTAL 78 86 EXTAL /ø HWR 84 ...
Page 36
Pin No. TFP-120 FP-128 Mode 1 104 114 V SS 105 115 TIOCB2/ TCLKD 106 116 TIOCA2 107 117 TIOCB1/ TCLKC 108 118 TIOCA1 109 119 P1 / ...
Page 37
Pin Functions Table 1-3 outlines the pin functions of the H8S/2355 Series. Table 1-3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø 16 Pin No. TFP-120 FP-128 I/O 1, 33, 5, 39, Input 52, ...
Page 38
Type Symbol Operating mode control MD 0 RES System control STBY BREQ BACK Pin No. TFP-120 FP-128 I/O 115 to 125 to Input 113 123 73 81 Input 75 83 Input 88 96 Input 87 95 Output ...
Page 39
Type Symbol Interrupts NMI IRQ7 to IRQ0 Address bus Data bus CS7 to Bus control CS0 AS RD HWR LWR WAIT LCAS 18 Pin No. TFP-120 FP-128 I ...
Page 40
Type Symbol 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 WDTOVF Watchdog timer (WDT) Pin No. ...
Page 41
Type Symbol Serial TxD2, communication TxD1, interface (SCI) TxD0 Smart Card RxD2, interface RxD1, RxD0 SCK2, SCK1 SCK0 A/D converter AN7 to AN0 ADTRG D/A converter* DA1, DA0 A/D converter AV CC and D/A converters ref 20 ...
Page 42
Type Symbol I/O ports ...
Page 43
Type Symbol I/O ports Note: * The H8S/2393 does not support a D/A converter. 22 Pin No. TFP-120 FP-128 I/O ...
Page 44
Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
Page 45
High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate 8/16/32-bit register-register add/subtract : 8-bit register-register multiply 16 ÷ 8-bit register-register divide 16 16-bit register-register multiply 32 ÷ 16-bit register-register divide Two CPU ...
Page 46
Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. Expanded address space Normal ...
Page 47
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum ...
Page 48
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in ...
Page 49
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown ...
Page 50
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
Page 51
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
Page 52
Address Space Figure 2-6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
Page 53
Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
Page 54
General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
Page 55
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
Page 56
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
Page 57
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ...
Page 58
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
Page 59
Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
Page 60
Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
Page 61
Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE, MOVTPE* Arithmetic ...
Page 62
Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @–ERn/@ERn+ @(d:32,ERn) @(d:16,ERn) @ERn Rn #xx 41 ...
Page 63
Rn #xx 42 ...
Page 64
Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General ...
Page 65
Table 2-3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM 44 Size* Function B/W/L (EAs) Rd, Rs Moves data between two general registers or between a general register and memory, or moves immediate ...
Page 66
Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Size* Function B/W/L Rd ± Rs Rd, Rd ± #IMM Performs addition or subtraction on data in two general registers immediate ...
Page 67
Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS 46 Size* Function B/W Rd ÷ Performs signed division on data in two general registers: either 16 bits ÷ 8 bits remainder or 32 bits ÷ 16 bits ...
Page 68
Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* Function B/W Rd, Rd Performs a logical AND operation on a general register and another general register or immediate ...
Page 69
Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR 48 Size* Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by ...
Page 70
Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Size* Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry ...
Page 71
Type Instruction Branch Bcc instructions JMP BSR JSR RTS 50 Size* Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC ...
Page 72
Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Size* Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes a transition to a power-down state. B/W (EAs) CCR, (EAs) Moves ...
Page 73
Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Note: * Size refers to the operand size. B: Byte W: Word L: Longword 52 Size* Function — if R4L 0 then Repeat @ER5+ R4L–1 R4L Until R4L = 0 else next; ...
Page 74
Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2-12 shows ...
Page 75
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
Page 76
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed ...
Page 77
Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
Page 78
If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding ...
Page 79
58 ...
Page 80
59 ...
Page 81
60 ...
Page 82
Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state ...
Page 83
End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition ...
Page 84
Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
Page 85
Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, ...
Page 86
Normal mode SP CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: *Ignored when returning. Figure 2-16 Stack Structure after Exception Handling (Examples) SP EXR Reserved* ...
Page 87
Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
Page 88
Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred "state." The memory cycle or bus ...
Page 89
Address bus AS RD HWR, LWR Data bus Figure 2-18 Pin States during On-Chip Memory Access 68 Bus cycle T1 Unchanged High High High High-impedance state ...
Page 90
On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access ...
Page 91
Address bus AS RD HWR, LWR Data bus Figure 2-20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a ...
Page 92
Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2355 Series has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width ...
Page 93
Note that the functions of each pin depend on the operating mode. The H8S/2355 Series can be used only in modes This means that the mode pins must be set to select one of these modes. Do ...
Page 94
System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode ...
Page 95
Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an ...
Page 96
Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part ...
Page 97
Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3-3 shows their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Mode 1 ...
Page 98
Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 On-chip RAM* H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed ...
Page 99
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 3 On-chip RAM* External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the ...
Page 100
Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 Reserved area H'F400 On-chip RAM* H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: * External addresses ...
Page 101
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 Reserved area H'FFF400 2 On-chip RAM* External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: ...
Page 102
Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 On-chip RAM* H'FBFF External address H'FC00 space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Notes: 1. When the EAE bit ...
Page 103
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE ...
Page 104
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or ...
Page 105
Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits ...
Page 106
Table 4-2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 ...
Page 107
Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2355 Series enters the reset state. A reset initializes the internal state of the CPU and the registers ...
Page 108
Reset Sequence The H8S/2355 Series enters the reset state when the RES pin goes low. To ensure that the H8S/2355 Series is reset, hold the RES pin low for at least power-up. To reset the H8S/2355 ...
Page 109
RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) ...
Page 110
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
Page 111
Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 47 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The ...
Page 112
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
Page 113
Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. Figure 4-5 (1) Stack Status ...
Page 114
Notes on Use of the Stack When accessing word data or longword data, the H8S/2355 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
Page 115
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2355 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can be set by ...
Page 116
Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input ISCR Internal interrupt request WOVI to TEI Interrupt controller Legend : IRQ sense control ...
Page 117
Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5-2 summarizes the registers ...
Page 118
Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 ...
Page 119
Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — Initial value : 0 R/W : — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts other than ...
Page 120
As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets the priority of the ...
Page 121
IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA 0 Initial value : R/W : R/W The ISCR registers are ...
Page 122
IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/W : R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of ...
Page 123
Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (47 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
Page 124
Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant ...
Page 125
Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) Reserved ADI (A/D conversion end) Reserved TGI0A (TGR0A input capture/compare match) TGI0B ...
Page 126
Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B ...
Page 127
Interrupt Source CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 ...
Page 128
Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2355 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. ...
Page 129
Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. ...
Page 130
Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority ...
Page 131
Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
Page 132
IRQ0 Yes Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in 112 Program execution status Interrupt generated? Yes Yes NMI No I=0 Yes No IRQ1 Yes Save PC and CCR I 1 Read vector address Branch to interrupt handling ...
Page 133
Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5-6 shows a ...
Page 134
Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in 114 Program execution status No Interrupt generated? Yes Yes NMI Level 6 interrupt? No Yes No Mask ...
Page 135
Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
Page 136
Figure 5-7 Interrupt Exception Handling 116 ...
Page 137
Interrupt Response Times The H8S/2355 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows ...
Page 138
Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
Page 139
Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
Page 140
DTC Activation by Interrupt 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Selection of a number of the above For details ...
Page 141
Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCEA to DTCEF ...
Page 142
Table 5-11 Interrupt Source Selection and Clearing Control Settings DTC DTCE DISEL Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling ...
Page 143
Section 6 Bus Controller 6.1 Overview The H8S/2355 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
Page 144
Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK WAIT Figure 6-1 Block Diagram of Bus Controller 124 Area decoder ABWCR ASTCR BCRH BCRL Bus controller Wait ...
Page 145
Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write CS0 to Chip select CS7 WAIT Wait ...
Page 146
Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 Modes Initial value : R/W Mode 4 Initial value : R/W ABWCR is an 8-bit ...
Page 147
Access State Control Register (ASTCR) Bit : 7 AST7 1 Initial value : R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets ...
Page 148
Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area enabled, and bits ...
Page 149
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
Page 150
WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
Page 151
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
Page 152
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted ...
Page 153
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access ...
Page 154
Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2355 reserved area* (in the H8S/2353) 1 Addresses H'010000 to H'01FFFF are external addresses (external expansion mode reserved area* (single-chip mode) ...
Page 155
H'000000 Area 0 (2Mbytes) H'1FFFFF H'200000 Area 1 (2Mbytes) H'3FFFFF H'400000 Area 2 (2Mbytes) H'5FFFFF H'600000 Area 3 (2Mbytes) H'7FFFFF H'800000 Area 4 (2Mbytes) H'9FFFFF H'A00000 Area 5 (2Mbytes) H'BFFFFF H'C00000 Area 6 (2Mbytes) H'DFFFFF H'E00000 Area 7 (2Mbytes) H'FFFFFF ...
Page 156
Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
Page 157
Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2355 Series memory interfaces comprise a basic ...
Page 158
Areas external expansion mode, all of areas external space. When area external space is accessed, the CS1 to CS6 pin signals respectively can be output. Only the basic bus ...
Page 159
Chip Select Signals The H8S/2355 Series can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal ...
Page 160
Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment ...
Page 161
Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one time is one byte ...
Page 162
Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
Page 163
Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed , the upper half (D The LWR pin is fixed high. Wait states cannot ...
Page 164
Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. ø Address ...
Page 165
Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D for the even address, and the lower half (D Wait states cannot ...
Page 166
Address bus CSn Read HWR LWR Write Note Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) ...
Page 167
Address bus CSn Read HWR LWR Write Note Figure 6-10 Bus Timing ...
Page 168
Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D for the even address, and the lower half (D Wait states ...
Page 169
Address bus CSn Read HWR LWR Write Note Figure 6-12 Bus Timing ...
Page 170
Address bus CSn Read HWR LWR Write Note Figure 6-13 Bus Timing ...
Page 171
Wait Control When accessing external space, the H8S/2355 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
Page 172
Figure 6-14 shows an example of wait state insertion timing. ø WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing ...
Page 173
Burst ROM Interface 6.5.1 Overview With the H8S/2355 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access ...
Page 174
T 1 ø Address bus CS0 AS RD Data bus Figure 6-15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) 154 Full access Only lower address changed Read data ...
Page 175
Address bus CS0 AS RD Data bus Figure 6-15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion ...
Page 176
Idle Cycle 6.6.1 Operation When the H8S/2355 Series accesses external space , it can insert a 1-state idle cycle (T bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when ...
Page 177
Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set idle cycle is inserted at the start of the write cycle. Figure 6-17 shows an example ...
Page 178
Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.18. In this case, with the setting for ...
Page 179
Pin States in Idle Cycle Table 6-5 shows pin states in an idle cycle. Table 6-5 Pin States in Idle Cycle Pins Pin State Contents of next bus cycle High impedance ...
Page 180
Bus Release 6.7.1 Overview The H8S/2355 Series can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there ...
Page 181
Pin States in External Bus Released State Table 6-6 shows pin states in the external bus released state. Table 6-6 Pin States in Bus Released State Pins Pin State High impedance ...
Page 182
Transition Timing Figure 6-19 shows the timing for transition to the bus-released state. CPU cycle T 0 ø Address bus Data bus AS RD HWR, LWR BREQ BACK Low level of BREQ pin is sampled at rise of T ...
Page 183
Usage Note When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release ...
Page 184
Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred ...
Page 185
Section 7 Data Transfer Controller 7.1 Overview The H8S/2355 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features The features of the DTC are: Transfer possible over ...
Page 186
Block Diagram Figure 7-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of ...
Page 187
Register Configuration Table 7-1 summarizes the DTC registers. Table 7-1 DTC Registers Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B ...
Page 188
Register Descriptions 7.2.1 DTC Mode Register A (MRA) MRA is an 8-bit register that controls the DTC operating mode. Bit : 7 SM1 Initial value : Unde- fined R/W : — Bits 7 and 6—Source Address Mode 1 and ...
Page 189
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 MD1 MD0 Description 0 0 Normal mode 1 Repeat mode 1 0 Block transfer mode 1 — Bit 1—DTC Transfer Mode Select ...
Page 190
DTC Mode Register B (MRB) Bit : 7 CHNE DISEL Initial value : Unde- fined R/W : — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With ...
Page 191
DTC Source Address Register (SAR) Bit : Initial value : Unde- Unde- Unde- fined fined fined R/W : — — — SAR is a 24-bit register that designates the source address of data to be transferred ...
Page 192
DTC Transfer Count Register B (CRB) Bit : Initial value : Unde- Unde- Unde- fined fined fined R/W : — — — CRB is a 16-bit register that designates the number of times data is to ...
Page 193
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 7.2.8 ...
Page 194
Module Stop Control Register (MSTPCR) Bit : Initial value : R/W : R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR ...
Page 195
Operation 7.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage ...
Page 196
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently ...
Page 197
Activation Sources The DTC operates when activated by an interrupt write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes ...
Page 198
When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the ...
Page 199
Table 7-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C ...
Page 200
Interrupt Source TGI3A (GR3A compare match/ input capture) TGI3B (GR3B compare match/ input capture) TGI3C (GR3C compare match/ input capture) TGI3D (GR3D compare match/ input capture) TGI4A (GR4A compare match/ input capture) TGI4B (GR4B compare match/ input capture) TGI5A (GR5A ...