CN8398KPF Conexant Systems, Inc., CN8398KPF Datasheet
CN8398KPF
Specifications of CN8398KPF
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CN8398KPF Summary of contents
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Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. CN8394/8395/8398 Quad/x16/Octal—T1/E1/J1 Framers The CN8394/8395/8398 is a family of single chip multiple framers for T1/E1/J1 and Integrated Service ...
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... Ordering Information Model Number Number of Framers CN8394ETF CN8394KTF CN8398EPF CN8398KPF CN8398EBG CN8398KBG CN8395EBG CN8395KBG CN0X660 Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Typical Quad T1/E1 Application Address Bus 12 Microprocessor Data Bus 8 Typical x16 T1/E1 Application Address Bus 12 Data Bus Microprocessor 8 2 Chip Selects N8398DSC Connection at DSX Levels CN8380 (Quad LIU) CN8394 (Quad T1/E1 Framer) ...
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Detailed Feature Summary Frame Alignment • Framed formats: – Independent transmit and receive framing modes – T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1) – E1: FAS/MFAS/FAS+CAS/MFAS+CAS • Maximum Average Reframe Time (MART) less than 50 ms • Transmitter alignment modes: – Align to system bus ...
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Data Links • Two full-featured data link controllers (DL1 and DL2): – 64-octet transmit and receive FIFOs – HDLC Message Oriented Protocol (MOP) – Unformatted data transfer – Unformatted circular buffer – End of message/buffer interrupt – Near full/empty interrupts ...
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N8398DSC Conexant Preliminary Information ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.2.5 Alarm Monitor 2.2.5.1 Loss of Frame 2.2.5.2 Loss of Signal 2.2.5.3 Receive Analog Loss of Signal 2.2.5.4 Alarm Indication Signal 2.2.5.5 Yellow Alarm 2.2.5.6 Multiframe YEL 2.2.5.7 Severely Errored Frame 2.2.5.8 Change of Frame Alignment 2.2.5.9 ...
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CN8394/8/5 Multiple T1/E1 Framer 2.4.4 Overhead Pattern Generation 2.4.4.1 Framing Pattern Generation 2.4.4.2 Alarm Generation 2.4.4.3 CRC Generation 2.4.4.4 Far-End Block Error Generation 2.4.5 Test Pattern Generation 2.4.6 Transmit Error Insertion 2.4.7 In-Band Loopback Code Generation 2.4.8 ZCS Encoder . ...
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Table of Contents 3.5 Interrupt Status Registers 004—Alarm 1 Interrupt Status (ISR7) 005—Alarm 2 Interrupt Status (ISR6) 006—Error Interrupt Status (ISR5) 007—Counter Overflow Interrupt Status (ISR4) 008—Timer Interrupt Status (ISR3) 009—Data Link 1 Interrupt Status (ISR2) 00A—Data Link 2 Interrupt ...
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CN8394/8/5 Multiple T1/E1 Framer 3.10 Performance Monitoring Registers 050—Framing Bit Error Counter LSB (FERR) 051—Framing Bit Error Counter MSB (FERR) 052—CRC Error Counter LSB (CERR) 053—CRC Error Counter MSB (CERR) 054—Line Code Violation Counter LSB (LCV) 055—Line Code Violation Counter ...
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Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CN8394/8/5 Multiple T1/E1 Framer 0DB—RSLIP Phase Status (RPHASE) 0DC—TSLIP Phase Status (TPHASE) 0DD—RAM Parity Status (PERR) 0E0–0FF—System Bus Per-Channel Control (SBCn 31) 100–11F—Transmit Per-Channel Control (TPCn 31) 120–13F—Transmit Signaling Buffer (TSIGn; n ...
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Table of Contents Appendix ...
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CN8394/8/5 Multiple T1/E1 Framer List of Figures 8398EVM—Evaluation Module, Octal T1/E1 ISDN PRI Board . . . . . . . . . . . . . . . . . . . . . . . . 2 Typical ...
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List of Figures Figure 2-26. Interrupt Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CN8394/8/5 Multiple T1/E1 Framer List of Tables Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4 ...
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List of Tables Table 3-23. Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Description 1.1 Overview The CN839x devices each contain multiple T1/E1 framers which provide the data access and framing portion of T1 and E1 physical layer interfaces: While the framers are identical, there are minor differences among the devices ...
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Product Description 1.1 Overview 1.1.3 LIU Serial Port The CN8394 and CN8398 devices include a serial interface which allows a microprocessor to indirectly communicate with a line interface unit such as the CN8380 Quad T1/E1 LIU. This interface allows ...
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CN8394/8/5 Multiple T1/E1 Framer 1.2 Pin Assignments The CN8394 is packaged in a 128-pin Quad Flat Pack (TQFP). The CN8395 is packaged in a 318-pin Ball Grid Array (BGA) multi-chip module (MCM). The CN8398 has two package alternatives: a 208-pin ...
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Product Description 1.2 Pin Assignments Figure 1-2. CN8394 128-Pinout Diagram TNEGO[4] / MSYNCO[ TCKI[4] 2 RCKI[4] 3 RPOSI[ ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 1-3. CN8395 318-Pinout Diagram ...
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Product Description 1.2 Pin Assignments Figure 1-4. CN8398 208-Pinout Diagram VGG 1 VSS 2 TSB3 / RSB3 TRST* 3 TMS 4 TDI 5 TDO 6 JTAG TCK 7 VDD 8 FSYNC[8] / TMSYNC[8] 9 TSBCKI[8] / TFSYNC[B] 10 TSB8 ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 1-5. CN8398 272-Pinout Diagram ...
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Product Description 1.2 Pin Assignments Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4 Pin Number 89 94 V15 J3 RPCMO[ W16 J4 RFSYNC[1]/RMSYNC[ Y17 J2 RSBCKI[ V16 — SIGFRZ[1] 93 ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4 Pin Number 29 202 B4 — RSIGO[3] / RDLO[3] — — — Y10 RSIGO[3] 30 203 A3 — RINDO[3] / RDLCKO[3] 31 204 C4 V9 ...
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Product Description 1.2 Pin Assignments Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8 Pin Number — 81 Y12 G4 RPCMO[5] — 82 W12 G2 RFSYNC[5] / RMSYNC[5] — 83 V12 G3 RSBCKI[5] — 84 Y13 — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8 Pin Number — — RSIGO[7] / RDLO[7] — — — W11 RSIGO[7] — — RINDO[7] / RDLCKO[7] — W12 ...
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Product Description 1.2 Pin Assignments Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12 Pin Number — — — F20 RPCMO[9] — — — F18 RFSYNC[9]/RMSYNC[9] — — — F19 RSBCKI[9] — — — F17 RSIGO[9] — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12 Pin Number — — — D9 RSIGO[12] — — — A9 TPCMI[12] — — — C9 TFSYNC[12]/TMSYCN[12] — — — B9 TSBCKI[12] — — — ...
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Product Description 1.2 Pin Assignments Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16 Pin Number — — — L18 TSIGI[14] — — — K16 TINDO[14] — — — B7 RPCMO[15] — — — B8 RFSYNC[15]/RMSYNC[15] — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — ...
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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( 119 — — — — — — — — 43 — — — — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-5. Pin Assignments ( — — — — — ...
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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( 100 101 102 103 — 104 107 105 106 108 109 110 112 115 113 114 116 117 118 120 123 121 122 124 ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-5. Pin Assignments ( 128 — — — — — — — — — — — — — — — — — — — — — — — ...
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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ...
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Product Description 1.2 Pin Assignments Table 1-5. Pin Assignments ( — — — — — — — — — — — — — — — — — — — — — — — — — — — ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-5. Pin Assignments ( — — — — N8398DSC Pin Number Pin Functions — D10 — NC — D9 — NC — D7 — NC — D5 — NC Conexant Preliminary Information 1.0 ...
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Product Description 1.2 Pin Assignments Figure 1-6. CN8394 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 1-7. CN8394 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I AS*(ALE*) Chip ...
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Product Description 1.2 Pin Assignments Figure 1-8. CN8398 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 1-9. CN8398 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I AS*(ALE*) Chip ...
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Product Description 1.2 Pin Assignments Figure 1-10. CN8395 Logic Diagram (Non-Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus mode I SYNCMD Motorola Bus mode I MOTO* Address Strobe I ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 1-11. CN8395 Logic Diagram (Multiplexed System Bus Mode) Hardware Reset I RST* System Clock I SYSCKI Processor Clock I MCLK Synchronous Bus Mode I SYNCMD Motorola Bus Mode I MOTO* Address Strobe I AS* (ALE*) ...
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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name RST* Hardware Reset SYSCKI System Clock MCLK Processor Clock SYNCMD Sync mode MOTO* Motorola Bus Mode A[10:0] Address Bus A[11:0] Address Bus ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name Microprocessor Interface (MPU) (Continued) CS* Chip Select DS*(RD*) Data Strobe or Read Strobe R/W*(WR*) Read/Write Direction or Write Strobe ONESEC One Second Timer ONESEC1 ...
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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name SERDI Serial Data Input SERCKO Serial Clock SERDO Serial Data Output SERCS* Serial Chip Select SERCS1* Serial Chip SERCS2* Selects TCKI[4:1] TX ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TCKO[4:1] TX Clock Output TCKO[8:1] TCKO[16:1] TNRZO[4:1] TX Non Return TNRZO[8:1] to Zero Data TNRZO[16:1] MSYNCO[4:1] TX Multiframe MSYNCO[8:1] Sync MSYNCO[16:1] RCKI[4:1] RX Clock ...
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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TSBCKI[4:1] TSB Clock Input TSBCKI[8:1] TSBCKI[16:1] TPCMI[4:1] TSB Data Input TPCMI[8:1] TPCMI[16:1] TSIGI[4:1] TSB Signaling TSIGI[8:1] Input TSIGI[16:1] TINDO[D:A] TSB Time Slot ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TMSYNC[4:1] TSB Multiframe TMSYNC[8:1] Sync TMSYNC[16:1] RSBCKI[4:1] RSB Clock Input RSBCKI[8:1] RSBCKI[16:1] RPCMO[4:1] RSB Data Output RPCMO[8:1] RPCMO[16:1] RINDO[D:A] RSB Time Slot RINDO[4:1] Indicator ...
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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name RSIGO[4:1] RSB Signaling RSIGO[8:1] Output RSIGO[16:1] RFSYNC[4:1] RSB Frame Sync RFSYNC[8:1] RFSYNC[16:1] RMSYNC[4:1] RSB Multiframe RMSYNC[8:1] Sync RMSYNC[16:1] SIGFRZ[4:1] Signaling Freeze SIGFRZ[8:1] ...
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CN8394/8/5 Multiple T1/E1 Framer Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TCK JTAG Clock TDI1, TDI2 JTAG Test Data Input TDI JTAG Test Data Input TMS JTAG Test mode Select TDO JTAG Test Data Output ...
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Product Description 1.2 Pin Assignments Table 1-6. Hardware Signal Definitions ( Pin Label Signal Name TSTO[16:1] Test Output TSTI[16:1] Test Input NOTE(S): ( CN8394 5 = CN8395 8 = CN8398 1. All RSB and TSB ...
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Circuit Description 2.1 Functional Block Diagram Figures 2-1 and multiplexed system bus modes. To show the details of these circuits, individual block diagrams of the functions listed below have been created and are placed, along with descriptions, throughout this ...
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Circuit Description 2.1 Functional Block Diagram Figure 2-1. Detailed Framer Block Diagram (Multiplexed System Bus Mode) MCLK MOTO* SYNCMD SYSCKI RNRZI[1] CS* (1) RPOSI[1] AS* (1) RNEGI[1] DS* R/W* DTACK* AD[7:0] RCKI[1] A[11:0] TCKO[1] INTR* ONESEC RST* (1) SERCS[1:0] ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-2. Detailed Framer Block Diagram (Non-multiplexed System Bus Mode) MCLK MOTO* SYNCMD SYSCKI RNRZI[1] CS* (1) RPOSI[1] AS* (1) RNEGI[1] DS* R/W* DTACK* AD[7:0] RCKI[1] A[11:0] TCKO[1] INTR* ONESEC RST* (1) SERCS[1:0] SERCLK SERDO (1) ...
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Circuit Description 2.2 Receiver 2.2 Receiver The Receiver (RCVR) inputs single rail NRZ data or decodes positive and negative rail NRZ data into single rail NRZ data. The RCVR, illustrated in Figure 2-3, consists of the following elements: Receive ...
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CN8394/8/5 Multiple T1/E1 Framer 2.2.2 In-Band Loopback Code Detection The in-band loopback code detector circuitry detects receive data with in-band codes of configurable value and length. These codes can be used to request loopback of terminal equipment signals or other ...
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Circuit Description 2.2 Receiver 2.2.3.1 Frame Bit Error The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments Counter every time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and NFAS (E1) ...
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CN8394/8/5 Multiple T1/E1 Framer 2.2.4.2 MFAS Error When CRC4 framing is enabled, MERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. ...
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Circuit Description 2.2 Receiver 2.2.5.1 Loss of Frame Receive Loss Of Frame (RLOF) is declared when the receive data stream does not meet the framing criteria specified in the Receiver Configuration register [RCR0; addr 040]. If the line rate ...
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CN8394/8/5 Multiple T1/E1 Framer 2.2.5.6 Multiframe YEL The criteria for Multiframe Yellow Alarm is described in Yellow Alarm Set/Clear ALM1, and the interrupt is available in ISR7. 2.2.5.7 Severely Errored A SEF is reported when the receive signal does not ...
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Circuit Description 2.2 Receiver 2.2.7 Receive Framing Two framers are in the receive data stream: an offline framer and an online frame status monitor. The offline framer recovers receive frame alignment; the online framer monitors frame alignment patterns and ...
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CN8394/8/5 Multiple T1/E1 Framer Table 2-1. Receive Framer Modes T1/E1N N8398DSC RFRAME[3:0] 0 000X FAS Only 0 001X FAS Only + BSLIP 0 010X FAS + CRC 0 011X FAS + CRC + BSLIP 0 100X FAS + CAS 0 ...
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Circuit Description 2.2 Receiver Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode FAS Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: • FAS pattern (0011011) is found in frame N. • Frame ...
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CN8394/8/5 Multiple T1/E1 Framer Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode SF Superframe alignment is recovered when: • Terminal frame alignment is recovered, identifying Ft bits. • Depends on SF submode: If JYEL, only Ft bits are ...
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Circuit Description 2.2 Receiver The offline framer waits until the current search is complete (see [FSTAT; addr 017]) before checking for pending LOF reframe requests. If both online framers have pending reframe requests, the offline framer aligns to the ...
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CN8394/8/5 Multiple T1/E1 Framer 2.2.8 External Receive Data Link (CN8394 and CN8398 Only) The External Data Link (DL3) provides signal access to any bit(s) in any time slot of all frames, odd frames, or even frames, including T1 framing bits. ...
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Circuit Description 2.2 Receiver 2.2.10 Receive Data Link The RCVR contains two independent data link controllers (DL1 and DL2) and a Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC formatted messages in ...
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CN8394/8/5 Multiple T1/E1 Framer The Receive Data Link FIFO #1 [RDL1; addr 0A8 bytes. The Receive FIFO buffer is formatted differently than the transmit FIFO buffer. The Receive buffer contains not only received messages, but also a status ...
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Circuit Description 2.2 Receiver Figure 2-5. Polled Receive Data Link Processing Wait N Milliseconds Message status contains number of message bytes (X) in FIFO. NOTE(S): 2-18 Receive Message Read Data Link Status If Yes FIFO EMPTY No Read Message ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-6. Interrupt-Driven Receive Data Link Processing Read Message Byte from FIFO and Discard Message status contains number of message bytes (X) in FIFO. NOTE(S): N8398DSC Interrupt Service Routine Interrupt Occurred Read Interrupt Status No Complete ...
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Circuit Description 2.2 Receiver 2.2.10.2 RBOP Receiver The Receive Bit-Oriented Protocol (RBOP) receiver receives BOP messages, including the ESF Yellow Alarm, which consists of repeated 16-bit patterns with an embedded 6-bit codeword as shown in this example: The BOP ...
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CN8394/8/5 Multiple T1/E1 Framer 2.3 System Bus Each framer provides high-speed, transmit and receive serial TDM interfaces. These interfaces can be configured as non-multiplexed, individual system buses, or they can be multiplexed internally or externally to provide 2xE1 (4096 Mbps) ...
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Circuit Description 2.3 System Bus 2.3.2 Externally Multiplexed Mode Externally Multiplexed mode allows any two, three, or four framers (in the same or different devices) to share a common high speed system bus (see The 4.096 and 8.192 MHz ...
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CN8394/8/5 Multiple T1/E1 Framer 2.3.3 Internally Multiplexed Mode Internally Multiplexed mode operation is very similar to Externally Multiplexed mode. The framers in each device are internally grouped into four-framer groups to allow an internally multiplexed mode (see 1 through 4 ...
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Circuit Description 2.3 System Bus Figure 2-8. Internally Multiplexed Configuration Examples Possible Internally Multiplexed Configurations 8.192 Mbps Framer 1 Two separte 8.192 Framer 2 Mbps buses is the typical application for Framer 3 Internally Multiplexed mode. Framer 4 8.192 ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-9 are provided in configured to output on the rising or falling edge of RSBCKI (see the Receive System Bus Configuration register [RSB_CR; addr 0D1]). Figure 2-9. RSB Waveforms RSBCKI Frame RPCMO ...
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Circuit Description 2.3 System Bus The 4.096 and 8.192 MHz bus modes contain multiple bus members ( which allow multiple T1/E1 signals to share the same system bus. This is done by interleaving the time slots ...
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CN8394/8/5 Multiple T1/E1 Framer The RSB maps line rate time slots to system bus time slots. The 24 (DS1 (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus time slots as ...
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Circuit Description 2.3 System Bus 2.3.4.1 Timebase The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the Receive System Bus Clock (RSBCKI). The RSBCK can be slaved to two different clock sources: Receive System Bus Clock Input (RSBCKI), or ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-13. T1 Line to E1 System Bus Time Slot Mapping Frame RNRZ A RPCMO NOTE(S): ( unassigned time slots ( frame ...
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Circuit Description 2.3 System Bus In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial 64-Bit Elastic throughput delay is 32 bits, one-half of the total depth. Similar to Normal mode, Elastic mode allows ...
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CN8394/8/5 Multiple T1/E1 Framer 2.3.4.4 Signaling Stack The Receive Signaling Stack (RSTACK) allows the processor to quickly extract signaling changes without polling every channel. RSTACK is activated on a per-channel basis by setting the Received Signaling Stack (SIG_STK) control bit ...
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Circuit Description 2.3 System Bus 2.3.5 Transmit System Bus The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling buffer, and transmit framer between the XMTR and the system bus. Figure 2-15. TSB Interface Block Diagram From ...
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CN8394/8/5 Multiple T1/E1 Framer Refer to definitions are provided in outputs can be configured to input data on the rising or falling edge of TSBCKI (see the Transmit System Bus Configuration register [TSB_CR; addr 0D4]. Figure 2-16. Transmit System Bus ...
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Circuit Description 2.3 System Bus The 4.096 and 8.192 MHz bus modes contain multiple bus members ( and D) of which one bus member is selected by the SBI [3:0] bits in the System Bus Interface Configuration ...
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CN8394/8/5 Multiple T1/E1 Framer 2.3.5.1 Timebase The TSB timebase synchronizes TPCMI, TFSYNC, TMSYNC, and TINDO with the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to three different clock sources: Transmit Clock Input (TCKI), Transmit System Bus Clock ...
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Circuit Description 2.3 System Bus In 64-bit Elastic mode, the slip buffer total depth is 64 bits and the initial 64-Bit Elastic throughput delay is 32 bits, or one-half of the total depth. Similar to Normal mode, Elastic mode ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-19. Transmit Framing and Timebase Alignment Options TPCMI TFSYNCI TMSYNCI TSB Offset TFSYNCO FSYNC MSYNC TMSYNCO TSB Timebase A TSB Aligns to TPCMI (EMBED = 0) B TSB Aligns to TX (TSB_ALIGN = 1) NOTE(S): ...
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Circuit Description 2.3 System Bus Note that the online framer's multiframe search status is not directly reported to the processor, but instead is monitored by examination of transmit error status: TMERR, TSERR, and TCERR [addr 00B]. If the system ...
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CN8394/8/5 Multiple T1/E1 Framer The status of the offline framer can be monitored using the Offline Framer Status register [FSTAT; addr 017]. The register reports the following: whether the offline framer is looking at the receive or transmit data streams ...
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Circuit Description 2.4 Transmitter 2.4 Transmitter The Transmitter (XMTR) inserts T1/E1 overhead data and outputs single rail NRZ data from the TSB or ZCS-encoded P and N rail NRZ data. The CN8395 only provides single rail NRZ transmit signals. ...
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CN8394/8/5 Multiple T1/E1 Framer 2.4.1 External Transmit Data Link (CN8394 and CN8398 Only) The External Data Link (DL3) allows the system to externally supply any bit(s) in any time slot in all frames, odd frames or even frames, including T1 ...
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Circuit Description 2.4 Transmitter DL1 and DL2 are configured identically, except for their offset in the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to 0B9. From this point on, ...
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CN8394/8/5 Multiple T1/E1 Framer 2.4.2.3 Time Slot and Time slot and bit selection is done through the DL1 Time Slot Enable [DL1_TS; Bit Selection addr 0A4] and DL1 Bit Enable [DL1_BIT; addr 0A5] registers. DL1_TS selects which frames and which ...
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Circuit Description 2.4 Transmitter 2.4.2.6 Programming The Transmit Data Link Controller can be programmed according to the system the Data Link Controller CPU bandwidth. For systems with sufficient CPU bandwidth, the data link status can be polled, and the ...
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CN8394/8/5 Multiple T1/E1 Framer Figure 2-23. Interrupt-Driven Transmit Data Link Processing Message 0x00 Block 1 0x20 Block 2 0x40 Block 3 0x60 Block 4 N8398DSC Main Line Code Transmit Message Write Block/Byte to FIFO Return Interrupt Service Routine Interrupt Occurred ...
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Circuit Description 2.4 Transmitter 2.4.2.7 PRM Generator In T1 applications, Performance Report Messages (PRMs) are HDLC messages containing path identification and performance monitoring information. If automatic performance report insertion is selected [AUTO_PRM; addr 0AA], a performance report is generated ...
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CN8394/8/5 Multiple T1/E1 Framer 2.4.4 Overhead Pattern Generation The transmit overhead generation circuitry provides the ability to insert all of the overhead associated with the Primary Rate Channel. The following types of overhead pattern generation are supported: Framing patterns, Alarm ...
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Circuit Description 2.4 Transmitter Yellow Alarm, also referred to as RAI (Remote Alarm Indication bit pattern Yellow Alarm Generation inserted into the transmit stream to alert far-end equipment that the local receiver cannot recover data. Yellow Alarm/RAI ...
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CN8394/8/5 Multiple T1/E1 Framer In E1 CAS framing modes, Multiframe Yellow Alarm is inserted into the transmit Multiframe Yellow Alarm stream to alert far-end equipment that local received multiframe alignment is not Generation recovered. E1 Multiframe Yellow Alarm is transmitted ...
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Circuit Description 2.4 Transmitter 2.4.5 Test Pattern Generation The transmit test pattern generation circuitry overwrites the transmit data with various test patterns and permits logical and frame-bit error insertion. This feature is particularly useful for system diagnostics, production testing, ...
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CN8394/8/5 Multiple T1/E1 Framer Change Of Frame Alignments (COFAs) are controlled by the TCOFA and BSLIP bits in the TERROR register. TCOFA commands a 1-bit shift in the location of the transmit frame alignment by deleting (or inserting) a 1-bit ...
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Circuit Description 2.4 Transmitter The HDB3 line code replaces four consecutive zeros by 000V or B00V code, where AMI pulse and bipolar violation (see encoder selects the code that will force the BPV ...
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CN8394/8/5 Multiple T1/E1 Framer 2.5 Microprocessor Interface The Microprocessor Interface (MPU) provides the capability to configure the device, read status registers and counters, and respond to interrupts (see Figure 2-25). The interface supports both the Intel 8051 and Motorola 68000-type ...
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Circuit Description 2.5 Microprocessor Interface 2.5.1 Address/Data Bus In Non-Multiplexed Address Mode, A[11:0] (A[10:0] for CN8394) provides the address for the register access. In Multiplexed Address Mode, A[11:8] (A[10:9] for CN8394) and AD[7:0] provide the address. In both modes, ...
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CN8394/8/5 Multiple T1/E1 Framer Using these registers, the microprocessor can process interrupts as follows: Interrupt service routine Read MIR and SER_STAT registers to determine which framer or framers 1. caused the interrupt or whether LIU serial operation occurred. For each ...
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Circuit Description 2.5 Microprocessor Interface 2.5.4 Device Reset The device contains four reset methods: Internal Power-On Reset (POR), 1. Hardware Reset which uses the RST* pin, 2. Global Software Reset which uses the GRESET bit in register FCR [addr ...
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CN8394/8/5 Multiple T1/E1 Framer 2.6 Loopbacks The device provides a complete set of loopbacks for diagnostics, maintenance, and troubleshooting for each framer. All loopbacks perform clock and data switching, if necessary. 2.6.1 Remote Line Loopback The line loopback loops the ...
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Circuit Description 2.6 Loopbacks 2.6.4 Local Framer Loopback The local framer loopback loops the transmit line encoder outputs to the receive line decoder inputs. Transmitter output is not affected by the activation of this loopback. The local framer loopback ...
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CN8394/8/5 Multiple T1/E1 Framer 2.7 Serial Interface The device provides a serial interface that allows the microprocessor to indirectly communicate with an attached LIU (such as the Conexant CN8380 Quad T1/E1 LIU). This interface allows the microprocessor to control and ...
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Circuit Description 2.8 Joint Test Access Group 2.8 Joint Test Access Group The device incorporates printed circuit board testability circuits in compliance with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and Boundary–Scan Architecture, commonly known as JTAG (Joint ...
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CN8394/8/5 Multiple T1/E1 Framer 2.8.2 Device Identification Register JTAG ID register consists of a 4-bit version, 16-bit part number, and 11-bit manufacturer number (see Table 2-9. CN8394 Device Identification JTAG Register (1) Version Part Number ...
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Circuit Description 2.8 Joint Test Access Group 2-62 Conexant Preliminary Information CN8394/8/5 Multiple T1/E1 Framer N8398DSC ...
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Registers 3.1 Address Map Registers shown with a default setting are reset to the indicated value following power up, software RESET (CRO; addr 001), GRESET (FCR; addr 080), or hardware reset (RST* pin). Addresses 000 (hex) to 1FF ...
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Registers 3.1 Address Map Table 3-3. Address Offset Map (CN8395) NOTE(S): 1. Global registers at 000 and 080–083 for framers 1–8 may be accessed at any of the first 8 offsets. 2. Global registers at 000 and 080–083 for ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-4. Address Map ( Address Block Acronym (Hex) 000 DID 080 FCR 081 MIR 082 MIE 083 TEST 001 CR0 003 IRR 004 ISR7 005 ISR6 006 ISR5 007 ISR4 008 ISR3 009 ...
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Registers 3.1 Address Map Table 3-4. Address Map ( Address Block Acronym (Hex) 022 SER_CTL 023 SER_DAT 024 SER_STAT 025 SER_CONFIG 026 RAM TEST 040 RCR0 041 RPATT 042 RLB 043 LBA 044 LBD 045 RALM 046 ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-4. Address Map ( Address Block Acronym (Hex) 070 TCR0 071 TCR1 072 TFRM 073 TERROR 074 TMAN 075 TALM 076 TPATT 077 TLB 078 LBP 07B TSA4 07C TSA5 07D TSA6 07E ...
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Registers 3.1 Address Map Table 3-4. Address Map ( Address Block Acronym (Hex) 0AF DL2_TS 0B0 DL2_BIT 0B1 DL2_CTL 0B2 RDL2_FFC 0B3 RDL2 0B4 RDL2_STAT 0B6 TDL2_FEC 0B7 TDL2_EOM 0B8 TDL2 0B9 TDL2_STAT 0BA DL_TEST1 0BB DL_TEST2 ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-4. Address Map ( Address Block Acronym (Hex) 100–11F TPCn 120–13F TSIGn 140–15F TSLIP_LOn 160–17F TSLIP_HIn ...
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Registers 3.2 Global Control and Status Registers 3.2 Global Control and Status Registers Global registers are applicable to all framers in the CN8394 and CN8398. There are two sets of global registers for the CN8395, one for each 8-framer ...
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CN8394/8/5 Multiple T1/E1 Framer The processor writes FCR at power-up to configure the system bus interface mode. Each SBIMODE[1:0] group of four framers can be configured as separate system bus interfaces internally multiplexed group. The group consisting ...
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Registers 3.2 Global Control and Status Registers 082—Master Interrupt Enable (MIE) CN8394 — — — CN8398 and CN8395 MIE[7] MIE[6] MIE[5] MIE is a global interrupt enable for each framer. Writing a one ...
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CN8394/8/5 Multiple T1/E1 Framer 3.3 Primary Control and Status Register 001—Primary Control Register (CR0) Unused bits are reserved and should be written RESET — RINCF Framer Reset—When written the microprocessor, RESET initiates ...
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Registers 3.3 Primary Control and Status Register Receiver Framer Mode—Establishes the offline framer's search criteria for recovery of frame RFRAME[3:0] alignment (reframe). Also works in conjunction with the RLOFA–RLOFD bits [addr 040] to establish the online framer's criteria for ...
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CN8394/8/5 Multiple T1/E1 Framer 3.4 Interrupt Control Register 003—Interrupt Request Register (IRR) An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the corresponding Interrupt Status Register [ISR7–ISR0; addr 004–00B]. IRR is latched ...
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Registers 3.4 Interrupt Control Register event 1 = active interrupt request PRBS Pattern or Transmit Framer Error—Indicates detection of PRBS test pattern sync or PATT detection of one or more transmit frame alignment pattern errors. Processor ...
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CN8394/8/5 Multiple T1/E1 Framer 3.5 Interrupt Status Registers An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding ...
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Registers 3.5 Interrupt Status Registers 004—Alarm 1 Interrupt Status (ISR7) All events reported in ISR7 are from dual-edge sources, except Receive Pulse Density Violation [RPDV]. Any transition of real-time status in Alarm 1 Status Register [ALM1; addr 047] forces ...
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CN8394/8/5 Multiple T1/E1 Framer 005—Alarm 2 Interrupt Status (ISR6) All events reported in ISR6 are from dual-edge sources, except the one-second timer [ONESEC] and Transmit Pulse Density Violation [TPDV]. Any transition of real-time status in the Alarm 2 Status Register ...
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Registers 3.5 Interrupt Status Registers 006—Error Interrupt Status (ISR5) All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the LATCH_ERR bit [addr 046] and triggers an interrupt if the ...
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CN8394/8/5 Multiple T1/E1 Framer 007—Counter Overflow Interrupt Status (ISR4) All count overflow events in ISR4 are from rising edge sources. Each event is latched active high when the respective error counter [addr 050–05A] reaches its maximum count value, but only ...
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Registers 3.5 Interrupt Status Registers Receive Signaling Stack—Indicates that one or more signaling bit changes were detected RSIG during the prior receive multiframe, and that new ABCD (robbed bit or CAS) signaling is available on the Receive Signaling Stack ...
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CN8394/8/5 Multiple T1/E1 Framer Message Transmitted TMSG1 is just beginning transmission. 00A—Data Link 2 Interrupt Status (ISR1) All events in ISR1 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR1. ...
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Registers 3.5 Interrupt Status Registers 00B—Pattern Interrupt Status (ISR0) All events in ISR0 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR0. Each event triggers an interrupt if the ...
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CN8394/8/5 Multiple T1/E1 Framer 3.6 Interrupt Enable Registers Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR bit, the associated MIR bit. While cleared, each IER bit allows that source to activate ...
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Registers 3.6 Interrupt Enable Registers 00E—Error Interrupt Enable Register (IER5) Unused bits are reserved and should be written TSLIP RSLIP — Enable TSLIP Interrupt TSLIP Enable RSLIP Interrupt RSLIP Enable CERR Interrupt CERR Enable ...
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CN8394/8/5 Multiple T1/E1 Framer 010—Timer Interrupt Enable Register (IER3 TSIG TMSYNC TMF Enable TSIG Interrupt TSIG Enable TMSYNC Interrupt TMSYNC Enable TMF Interrupt TMF Enable TFRAME Interrupt TFRAME Enable RSIG Interrupt RSIG Enable RMSYNC Interrupt RMSYNC Enable ...
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Registers 3.6 Interrupt Enable Registers 012—Data Link 2 Interrupt Enable Register (IER1 RBOP RFULL2 RNEAR2 Enable RBOP Interrupt RBOP Enable RFULL Interrupt RFULL2 Enable RNEAR Interrupt RNEAR2 Enable RMSG Interrupt RMSG2 Enable TDLERR Interrupt TDLERR2 Enable ...
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CN8394/8/5 Multiple T1/E1 Framer 3.7 Primary Control and Status Registers 014—Loopback Configuration Register (LOOP) Unused bits are reserved and should be written — — — Enable Remote Payload Loopback—Payload from receiver replaces payload on transmitter ...
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Registers 3.7 Primary Control and Status Registers 015—External Data Link Time Slot (DL3_TS) DL3_TS works in conjunction with the DL3_BIT Register [addr 016] to determine which transmit time slots are supplied from the TDLI pins and which receive and ...
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CN8394/8/5 Multiple T1/E1 Framer 016—External Data Link Bit (DL3_BIT DL3_BIT[7] DL3_BIT[6] DL3_BIT[5] External Data Link Bit Select—Enables receive (RDLCKO) and transmit (TDLCKO) clock DL3_BIT[7:0] pulse outputs during the selected time slot bits. DL3_BIT and the DL3_TS Register ...
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Registers 3.7 Primary Control and Status Registers Framer Search Timeout—Cleared when the offline framer transitions to its ACTIVE state. If TIMEOUT multiple frame candidates exist over the entire mode-dependent timeout interval (refer to Table 3-8), TIMEOUT is latched active ...
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CN8394/8/5 Multiple T1/E1 Framer 018—Programmable Input/Output (PIO RMSYNC_EN RDL_IO TMSYNC_EN Enable RMSYNC—Select which signal is present on bimodal RSYNC pin. When active, RMSYNC_EN receiver multiframe sync (RMSYNC) is enabled. Otherwise, receiver frame sync RFSYNC is enabled. Note ...
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Registers 3.7 Primary Control and Status Registers Bidirectional TFSYNC Input/Output Mode—TFSYNC_IO programming is dependent on TFSYNC_IO transmit framer and system bus modes as shown TFSYNC input 1 = TFSYNC output Bidirectional TMSYNC Input/Output mode—TMSYNC_IO programming is ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-11. Common RFSYNC and RMSYNC Configurations Conditions RFSYNC Thru = 0 [RSIG_CR; IN addr 0D7] IN OUT OUT Thru = 1 [RSIG_CR; IN addr 0D7] OUT 019—Programmable Output Enable (POE) Unused bits are reserved and ...
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Registers 3.7 Primary Control and Status Registers 01A—Clock Input Mux (CMUX) Unused bits are reserved and should be written — RSBCK — RSBCK Source Select—Internal clock mux selects from one of two clock signals ...
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CN8394/8/5 Multiple T1/E1 Framer 021—Receive Line Code Status (RSTAT) Unused bits are reserved and should be written — — ZCSUB Zero Code Substitution—Indicates one or more B8ZS/HDB3 substitution patterns have been ZCSUB detected on receiver ...
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Registers 3.8 Serial Interface Registers 3.8 Serial Interface Registers These registers are not used on the CN8395 device. 022—Serial Control (SER_CTL) Writing to SER_CTL initiates a serial interface read or write operation. During a write operation, a 16-bit word, ...
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CN8394/8/5 Multiple T1/E1 Framer 025—Serial Configuration (SER_CONFIG) Unused bits are reserved and should be written SER_CS SER_CLK — Serial Interface Chip Select 1 SER_CS 0 = sets external SERCS1* signal low 1 = sets external ...
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Register 3.9 Receiver Registers 3 3.9 Receiver Registers 040—Receiver Configuration (RCR0 RAMI RABORT RFORCE Receive AMI Encoded Inputs—Disables B8ZS/HDB3 decoding for AMI formatted receive RAMI signals. Otherwise, ZCS decoder replaces 000VB0VB code (B8ZS) with 8 zeros ...
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CN8394/8/5 Multiple T1/E1 Framer Receive B8ZS/HDB3 Zero Code Substitution (affects only BPV/LCV/EXZ counting)—When RZCS set, the ZCS decoder does not include bipolar violations received as part of a B8ZS/HDB3 code in the LCV error count [addr 054, 055]. Otherwise, all ...
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Register 3.9 Receiver Registers Table 3-12. Receive PRBS Test Pattern Measurements ( FRAMED ZLIMIT RPATT PRBS Zero Limit—Determines the ...
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CN8394/8/5 Multiple T1/E1 Framer Loopback Activate Code Length—Selects the number of loopback pattern bits from LBA UP_LEN[1:0] [addr 043] that are compared to received data. This is done in order to determine whether a Loopback Activate Code [LOOPUP; addr 048] ...
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Register 3.9 Receiver Registers 045—Receive Alarm Signal Configuration (RALM) Unused bits are reserved and should be written — DIS_LCV FS_NFAS Disable LCV indication and counting. Primarily used in configurations where receive data is DIS_LCV ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-13. Receive Yellow Alarm Set/Clear Criteria ( Mode YJ Set for 1 multiframe (1.5 ms) if frame 12 contains Fs bit = 1. Cleared for 1 multiframe if frame 12 contains Fs bit ...
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Register 3.9 Receiver Registers 046—Alarm/Error/Counter Latch Configuration (LATCH) Unused bits are reserved and should be written — — — Stop Error Count during RLOF/RLOS/RAIS—If enabled, error count registers [addr 050–057] STOP_CNT are suspended at ...
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CN8394/8/5 Multiple T1/E1 Framer 047—Alarm 1 Status (ALM1) Unused bits are reserved and should be written to 0. ALM1 reports current status of receive alarms. Any change in the current status activates the corresponding interrupt status bit [ISR7; addr 004]. ...
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Register 3.9 Receiver Registers Receive Alarm Indication Signal—Criteria for detection and clearance of RAIS per ITU G.775 RAIS and ANSI T1.231. Mode Receive Loss of Signal or Receive Clock—Reports loss of receive clock (RCKI) or ...
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CN8394/8/5 Multiple T1/E1 Framer Receive Loss of Frame Alignment—Real-time or integrated RLOF status depends on selected RLOF receive framer mode, out of frame criteria [RLOFA–RLOFD; addr 040], and integration mode [RLOF_INTEG; addr 045]. Refer to frame bits are monitored. Refer ...
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Register 3.9 Receiver Registers 049—Alarm 3 Status (ALM3) Reports real-time status of the receive framer (not affected by ONESEC latch mode), and miscellaneous latched error status (SEF and RMAIS). Any change of the logical OR of (FRED or MRED ...
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CN8394/8/5 Multiple T1/E1 Framer 3.10 Performance Monitoring Registers If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective Performance Monitoring counter, the counter is allowed to roll over after reaching its maximum count value. If the overflow ...
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Register 3.10 Performance Monitoring Registers 054—Line Code Violation Counter LSB (LCV LCV[7] LCV[6] LCV[5] BPV and EXZ (if EXZ_LCV enabled) Error Count LCV[7:0] 055—Line Code Violation Counter MSB (LCV) If LATCH_CNT [addr 046] is inactive, reading ...
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CN8394/8/5 Multiple T1/E1 Framer 059—PRBS Bit Error Counter MSB (BERR BERR Count (suspended if BSTART = 0) BERR[11:8] 05A—SEF/FRED/COFA Alarm Counter (AERR) Reading AERR clears the SEF[1:0], COFA[1:0] and FRED[3:0] count values ...
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Register 3.11 Receive Sa-Byte Buffers 3.11 Receive Sa-Byte Buffers Five receive Sa-Byte buffers [RSA4–RSA8] are double-buffered. All five registers are updated with the Sa-bits received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr 008]. Bit ...
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CN8394/8/5 Multiple T1/E1 Framer 05D—Receive Sa6 Byte Buffer (RSA6 RSA6[7] RSA6[6] RSA6[5] Sa6 bit received in frame 15 RSA6[7] Sa6 bit received in frame 13 RSA6[6] Sa6 bit received in frame 11 RSA6[5] Sa6 bit received in ...
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Register 3.11 Receive Sa-Byte Buffers 05F—Receive Sa8 Byte Buffer (RSA8 RSA8[7] RSA8[6] RSA8[5] Sa8 bit received in frame 15 RSA8[7] Sa8 bit received in frame 13 RSA8[6] Sa8 bit received in frame 11 RSA8[5] Sa8 bit ...
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CN8394/8/5 Multiple T1/E1 Framer 3 3.12 Transmitter Registers 070—Transmit Framer Configuration (TCR0) TCR0 selects the offline framer's criteria for recovery of transmit frame alignment and determines the output of transmit frame and alarm formatters overhead bits. In addition, TCR0 works ...
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Register 3.12 Transmitter Registers Frame formatter generates Ft, Fs, FPS, FAS, MFAS, and CRC bits. Alarm formatter generates TFRAME[3:0] YB2, YJ, Y0, and Y16 bits. Frame and alarm overhead formats are selected by TFRAME[3:0] and T1/E1N settings as given ...
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CN8394/8/5 Multiple T1/E1 Framer Table 3-16. T1 Transmit Framer Modes (T1/E1N = 1) TFRAME Framer Mode 0000 FT Only Ones 0100 SF 0101 SF + JYEL 100X SLC 0001 ESF + No CRC 1100 ESF + Mimic CRC 1101 ESF ...
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Register 3.12 Transmitter Registers Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment Mode FT Only Terminal Frame Alignment is recovered when: One and only one valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ...
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CN8394/8/5 Multiple T1/E1 Framer 071—Transmitter Configuration (TCR1 TNRZ TABORT TFORCE Transmit NRZ Data—Transmit dual-rail unipolar outputs TPOSO/TNEGO are replaced by TNRZ non-return to zero unipolar data (TNRZO) and transmit multiframe sync (MSYNCO). Both outputs are clocked on ...
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Register 3.12 Transmitter Registers Transmit Loss Of Frame Criteria—Determines the number of frame errors that the online TLOFC–TLOFA framer must detect before declaring loss of frame alignment [TLOF; addr 048]. Refer to TFRAME [addr 070] to find which frame ...
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CN8394/8/5 Multiple T1/E1 Framer 072—Transmit Frame Format (TFRM) TFRM controls the insertion of overhead bits generated by transmit frame and alarm formatters. Bypassed overhead bits flow transparently from TPCMI system bus input through TSLIP buffer. Unused bits are reserved and ...
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Register 3.12 Transmitter Registers 073—Transmit Error Insert (TERROR) Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment applications. Writing a one to any TERROR bit injects a single occurrence of the respective error on ...
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CN8394/8/5 Multiple T1/E1 Framer Inject Line Code Violation—Injects a single LCV error, depending on line mode and ZCS TVERR selected mode, the LCV injector waits for transmission of two consecutive pulses on the data output before performing BPV ...
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Register 3.12 Transmitter Registers 075—Transmit Alarm Signal Configuration (TALM) Unused bits are reserved and should be written — AISCLK AUTO_MYEL Enable Automatic ACKI Switching—When AISCLK is active and the clock monitor reports a AISCLK ...
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CN8394/8/5 Multiple T1/E1 Framer Manual/Automatic Transmit Alarm Indication Signal—When activated manually (TAIS) or AUTO_AIS /TAIS automatically (AUTO_AIS), the alarm formatter replaces all data output on TPOSO/TNEGO/TNRZO with an unframed all ones signal (AIS). This includes replacing data from the receiver ...
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Register 3.12 Transmitter Registers Table 3-21. Transmit PRBS Test Pattern Measurements FRAMED ZLIMIT TPATT ...
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CN8394/8/5 Multiple T1/E1 Framer 078—Transmit Inband Loopback Code Pattern (LBP) Unused bits are reserved and should be written LBP[1] LBP[2] LBP[3] First bit transmitted LBP[1] Second bit transmitted LBP[2] Third bit transmitted LBP[3] Fourth bit ...
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Register 3.13 Transmit Sa-Byte Buffers 3.13 Transmit Sa-Byte Buffers Five transmit Sa-Byte buffers (TSA4–TSA8) are used to insert Sa-bits in TS0. The entire group of 40 bits is sampled every 16 frames, coincident with the TMF interrupt boundary [addr ...
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CN8394/8/5 Multiple T1/E1 Framer 07D—Transmit Sa6 Byte Buffer (TSA6 TSA6[7] TSA6[6] TSA6[5] Sa6 bit transmitted in frame 15 TSA6[7] Sa6 bit transmitted in frame 13 TSA6[6] Sa6 bit transmitted in frame 11 TSA6[5] Sa6 bit transmitted in ...
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Register 3.13 Transmit Sa-Byte Buffers 07F—Transmit Sa8 Byte Buffer (TSA8 TSA8[7] TSA8[6] TSA8[5] Sa8 bit transmitted in frame 15 TSA8[7] Sa8 bit transmitted in frame 13 TSA8[6] Sa8 bit transmitted in frame 11 TSA8[5] Sa8 bit ...
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CN8394/8/5 Multiple T1/E1 Framer 3 3.14 Bit-Oriented Protocol Registers The Bit Oriented Protocol (BOP) transceiver sends and receives BOP messages, including ESF Yellow Alarm. These messages consist of repeated 16-bit patterns with an embedded 6-bit codeword. The BOP message channel ...
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Register 3.14 Bit-Oriented Protocol Registers TBOP Message Length—Selects the number of repeated 16-bit patterns sent as a single TBOP_LEN[1:0] message when a TBOP [addr 0A1] codeword is written. Another message, with the same or different codeword value, can be ...
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CN8394/8/5 Multiple T1/E1 Framer 0A2—Receive BOP Codeword (RBOP RBOP_LOST RBOP_VALID RBOP[5] Previous Message Overwritten—Activated when RBOP is updated and RBOP_VALID is RBOP_LOST already set, indicating that the previous codeword was never read by the processor ...
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Register 3.15 Data Link Registers 3 3.15 Data Link Registers Each framer contains two independent Data Link Controllers (DL1, DL2), which are programmed to send and receive HDLC formatted or unformatted serial data over any combination of bits within ...
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CN8394/8/5 Multiple T1/E1 Framer 0A5—DL1 Bit Enable (DL1_BIT DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1 Bit Select—Works in conjunction with DL1_TS [addr 0A4] to select one or more time DL1_BIT[7:0] slot bits for data link input and output. Any combination ...
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Register 3.15 Data Link Registers Non-FCS mode passes all message bits that exist between the opening and closing FLAG characters through the FIFOs, without generating or checking FCS bits. Non-FCS mode allows the processor to generate and check the ...
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CN8394/8/5 Multiple T1/E1 Framer For example, SLC applications monitor Fs bits during even frames for a total of 36 bits monitored out of 72 frames. Using Pack6 mode, that group bits from each SLC multiframe can be ...
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Register 3.15 Data Link Registers 0A8—Receive Data Link FIFO #1 (RDL1) Two different read byte values are supplied: WORD0 equals message status, and WORD1 equals message data. The processor determines which byte value is located in the FIFO by ...
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CN8394/8/5 Multiple T1/E1 Framer WORD1: Message Data RDL1[7] RDL1[6] RDL1[5] Receive Message Data—Filled by the receiver data link, from LSB to MSB, with bits from the RDL1[7:0] selected channel. Processor reads 8-bit FIFO data during HDLC and ...
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Register 3.15 Data Link Registers Receive FIFO Full—Indicates data link has completely filled 64 byte locations in the receive RFULL1 FIFO. In all cases, RFULL1 is an error, indicating the processor didn’t keep pace with the receiver and indicates ...
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CN8394/8/5 Multiple T1/E1 Framer Automatic SL Bit Insertion—RFSLIP error status is encoded into the transmit PRM contents. AUTO_SL Or, the PRM_SL bit value supplied by the processor is sent send PRM_SL value in SL bit 1 = send ...
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Register 3.15 Data Link Registers 0AC—TDL #1 End Of Message Control (TDL1_EOM) Unused bits are reserved and should be written — — — End of Transmit Message. Writing any data value to TDL1_EOM marks ...