HD6433042F HITACHI, HD6433042F Datasheet
HD6433042F
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HD6433042F Summary of contents
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OMC 942723026 H8/3042, H8/3041, H8/3040 H8/3042 Series Hardware Manual ADE-602-067 ...
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The H8/3042 Series is a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed ...
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Section 1 Overview 1.1 Overview......................................................................................................................... 1.2 Block Diagram................................................................................................................ 1.3 Pin Description ............................................................................................................... 1.3.1 Pin Arrangement............................................................................................. 1.3.2 Pin Functions .................................................................................................. 1.4 Pin Functions .................................................................................................................. 10 Section 2 CPU ............................................................................................................... 15 2.1 Overview......................................................................................................................... 15 2.1.1 Features........................................................................................................... 15 2.1.2 Differences from H8/300 CPU ...
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Basic Operational Timing ............................................................................................... 51 2.9.1 Overview......................................................................................................... 51 2.9.2 On-Chip Memory Access Timing................................................................... 51 2.9.3 On-Chip Supporting Module Access Timing ................................................. 53 2.9.4 Access to External Address Space.................................................................. 54 Section 3 MCU Operating Modes 3.1 Overview......................................................................................................................... 55 3.1.1 Operating ...
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Register Configuration.................................................................................... 81 5.2 Register Descriptions...................................................................................................... 82 5.2.1 System Control Register (SYSCR)................................................................. 82 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 83 5.2.3 IRQ Status Register (ISR) .............................................................................. 90 5.2.4 IRQ Enable Register (IER)............................................................................. 91 5.2.5 IRQ ...
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Connection to Dynamic RAM and Pseudo-Static RAM ................................ 139 6.4.2 Register Write Timing .................................................................................... 139 6.4.3 Input Timing........................................................................................ 141 BREQ Section 7 Refresh Controller 7.1 Overview......................................................................................................................... 143 7.1.1 Features........................................................................................................... 143 7.1.2 Block Diagram................................................................................................ 144 7.1.3 Input/Output Pins............................................................................................ 145 7.1.4 ...
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Overview......................................................................................................... 202 8.4.2 I/O Mode......................................................................................................... 204 8.4.3 Idle Mode........................................................................................................ 206 8.4.4 Repeat Mode................................................................................................... 209 8.4.5 Normal Mode.................................................................................................. 212 8.4.6 Block Transfer Mode ...................................................................................... 215 8.4.7 DMAC Activation .......................................................................................... 220 8.4.8 DMAC Bus Cycle........................................................................................... 222 8.4.9 Multiple-Channel Operation........................................................................... 228 8.4.10 ...
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Overview......................................................................................................... 256 9.5.2 Register Descriptions...................................................................................... 257 9.5.3 Pin Functions in Each Mode........................................................................... 259 9.5.4 Input Pull-Up Transistors................................................................................ 261 9.6 Port 5............................................................................................................................... 262 9.6.1 Overview......................................................................................................... 262 9.6.2 Register Descriptions...................................................................................... 262 9.6.3 Pin Functions in Each Mode........................................................................... 264 9.6.4 Input Pull-Up ...
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Timer Synchro Register (TSNC) .................................................................... 314 10.2.3 Timer Mode Register (TMDR)....................................................................... 316 10.2.4 Timer Function Control Register (TFCR) ...................................................... 319 10.2.5 Timer Output Master Enable Register (TOER) .............................................. 321 10.2.6 Timer Output Control Register (TOCR)......................................................... 324 10.2.7 Timer Counters ...
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Port B Data Register (PBDR) ......................................................................... 406 11.2.5 Next Data Register A (NDRA)....................................................................... 407 11.2.6 Next Data Register B (NDRB) ....................................................................... 409 11.2.7 Next Data Enable Register A (NDERA) ........................................................ 411 11.2.8 Next Data Enable Register B (NDERB)......................................................... 412 ...
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Register Configuration.................................................................................... 446 13.2 Register Descriptions...................................................................................................... 447 13.2.1 Receive Shift Register (RSR) ......................................................................... 447 13.2.2 Receive Data Register (RDR)......................................................................... 447 13.2.3 Transmit Shift Register (TSR)........................................................................ 448 13.2.4 Transmit Data Register (TDR) ....................................................................... 448 13.2.5 Serial Mode Register (SMR) .......................................................................... ...
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Input/Output Pins............................................................................................ 522 15.1.4 Register Configuration.................................................................................... 522 15.2 Register Descriptions...................................................................................................... 523 15.2.1 D/A Data Registers 0 and 1 (DADR0/1) ........................................................ 523 15.2.2 D/A Control Register (DACR) ....................................................................... 523 15.3 Operation ........................................................................................................................ 525 Section 16 RAM ............................................................................................................. 527 16.1 Overview......................................................................................................................... ...
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Software Standby Mode ................................................................................................. 553 19.4.1 Transition to Software Standby Mode ............................................................ 553 19.4.2 Exit from Software Standby Mode ................................................................. 553 19.4.3 Selection of Waiting Time for Exit from Software Standby Mode ................ 554 19.4.4 Sample Application of Software ...
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C.4 Port 4 Block Diagram ..................................................................................................... 703 C.5 Port 5 Block Diagram ..................................................................................................... 704 C.6 Port 6 Block Diagrams.................................................................................................... 705 C.7 Port 7 Block Diagrams.................................................................................................... 709 C.8 Port 8 Block Diagrams.................................................................................................... 710 C.9 Port 9 Block Diagrams.................................................................................................... 713 C.10 Port ...
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... In addition to the masked-ROM versions of the H8/3042 Series, the H8/3042 has a ZTAT™* version with user-programmable on-chip PROM. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Table 1-1 summarizes the features of the H8/3042 Series. Note: * ZTAT (Zero Turn-Around Time trademark of Hitachi, Ltd. Section 1 Overview 1 ...
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Table 1-1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 16 MHz ...
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Table 1-1 Features (cont) Feature Description Refresh DRAM refresh controller • Directly connectable to 16-bit-wide DRAM • CAS-before-RAS refresh • Self-refresh mode selectable Pseudo-static RAM refresh • Self-refresh mode selectable Usable as an interval timer DMA controller Short address mode ...
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... Other features • On-chip clock oscillator Product lineup Model (5-V) HD6473042TF HD6473042VTF 100-pin TQFP (TFP-100B) PROM HD6473042F HD6433042TF HD6433042VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433042F HD6433041TF HD6433041VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433041F HD6433040TF HD6433040VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433040F Address Address Initial Bus Max ...
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Block Diagram Figure 1-1 shows an internal block diagram EXTAL XTAL ø STBY RES RESO NMI P6 /LWR 6 P6 /HWR /BACK 2 P6 /BREQ ...
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Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3042 Series TIOCA /TP / TIOCB /TP / TIOCA /TP / ...
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Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the pin assignments in each mode. Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin Mode 1 Mode 2 No. Mode ...
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Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont) Pin Mode 1 Mode 2 No. Mode ...
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Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont) Pin Mode 1 Mode 2 No. Mode HWR HWR 71 LWR LWR ...
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Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø Operating mode control Pin No. I/O Name and Function 1, 35, 68 ...
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Table 1-3 Pin Functions (cont) Type Symbol System control RES RESO STBY BREQ BACK Interrupts NMI IRQ to 5 IRQ 0 Address bus Data bus Bus control ...
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Table 1-3 Pin Functions (cont) Type Symbol RFSH Refresh controller HWR LWR DMA DREQ , 1 controller DREQ 0 (DMAC) TEND , 1 TEND 0 16-bit TCLKD to integrated TCLKA timer-unit TIOCA to 4 (ITU) TIOCA 0 ...
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Table 1-3 Pin Functions (cont) Type Symbol Programmable timing pattern TP 0 controller (TPC) Serial com- TxD , 1 munication TxD 0 interface (SCI) RxD , 1 RxD 0 SCK , 1 SCK 0 A/D converter AN ...
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Table 1-3 Pin Functions (cont) Type Symbol I/O ports ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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High-speed operation — All frequently-used instructions execute in two to four states — Maximum clock frequency: — 8/16/32-bit register-register add/subtract: 125 ns — 8 8-bit register-register multiply: — 16 ÷ 8-bit register-register divide: — 16 16-bit register-register multiply: — ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. See figure 2-1. CPU operating modes Normal mode Advanced mode Figure ...
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Address Space Figure 2-2 shows a simple memory map for the H8/3042 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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General Data Type Register Word data Rn Word data En Longword data ERn Legend ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant ...
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Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Address 7 Address Address ...
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Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2-1. Table 2-1 Instruction Classification Function Instruction Data transfer MOV, PUSH Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
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Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Function Instruction #xx Rn MOV BWL BWL BWL Data transfer POP, PUSH — — MOVFPE, — — MOVTPE ADD, ...
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Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...
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Table 2-3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in the ...
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Table 2-4 Arithmetic Operation Instructions Instruction Size* Function ADD, B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot be subtracted ...
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Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* Function DIVXU B/W Rd ÷ Rs Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits 16-bit quotient and 16-bit remainder. DIVXS B/W Rd ÷ Rs Performs ...
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Table 2-5 Logic Operation Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a general register and ...
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Table 2-7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 ...
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Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function BOR B C (<bit-No.> of <EAd>) ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B ...
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Table 2-8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) Moves the source operand contents to the ...
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Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — repeat @ER5+ until else next ≠ 0 then EEPMOV.W — repeat @ER5+ until else next; Transfers a data block according to parameters set ...
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Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates ...
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Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used ...
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Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and ...
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Table 2-12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF (1048320 to 1048575) 16 bits (@aa:16) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) 24 bits (@aa:24) H'00000 to H'FFFFF ...
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Specified by @aa:8 Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. ...
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Table 2-13 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn)/@(d:24, ERn disp 4 Register indirect with post-increment ...
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Table 2-13 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs 6 Immediate #xx:8, #xx:16, or #xx:32 op IMM 7 Program-counter relative @(d:8, PC) or @(d:16, PC) ...
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Table 2-13 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format Memory indirect @@aa Normal mode op abs Advanced mode op abs Legend r, rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 ...
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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...
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Reset Exception Interrupt sources Trap instruction Figure 2-12 Classification of Exception Sources End of bus release Bus request Bus-released state End of exception handling Exception-handling state RES = 1 *1 Reset state Notes: 1. From any state except hardware standby ...
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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling ...
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Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an ...
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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or bus ...
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Address bus AS RD HWR LWR , , , Figure 2-16 Pin States during On-Chip Memory Access Address High High impedance 52 H8/3003 U.M. '93 Fig. 2-16 ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus bits wide, depending on the register being accessed. Figure 2-17 shows the on-chip supporting module access timing. Figure ...
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Address bus AS RD HWR LWR , , , Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3042 Series has seven operating modes (modes that are selected by the mode pins ( indicated in table 3-1. The input ...
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Mode externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. Modes 6 and 7 are single-chip ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3042 Series. Bit 7 — Initial value 1 Read/Write — Reserved bits Note: Determined by pins ...
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System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3042 Series. 7 SSBY STS2 0 R/W R/W Standby timer select These bits select the waiting time at recovery from software ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. ...
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Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas least one area ...
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Pin Functions in Each Operating Mode The pin functions of ports and port A vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode. Table 3-3 Pin Functions in Each Mode ...
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Modes 1 and 2 (1-Mbyte modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 H'7FFFF space H'80000 Area 4 H'9FFFF H'A0000 Area 5 ...
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Mode 5 (expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF H'0FFFF H'10000 Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 H'7FFFF space H'80000 Area 4 H'9FFFF H'A0000 ...
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Modes 1 and 2 (1-Mbyte modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area 5 ...
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Mode 5 (expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF H'0BFFF H'0C000 Reserved *1 H'0FFFF H'10000 Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 ...
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Modes 1 and 2 (1-Mbyte modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 H'7FFFF space H'80000 Area 4 H'9FFFF H'A0000 Area 5 ...
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Mode 5 (expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF Reserved *1 H'10000 Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or ...
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Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset Exception • Interrupts sources • Trap ...
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Reset 4.2.1 Overview A reset is the highest-priority exception. When the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the ...
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RES Address (1) bus RD HWR LWR High , ( (1), (3), (5), (7) Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003 (2), (4), (6), (8) ...
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RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'00000, (3) = H'00002 (2), (4) Start address (contents of reset vector) (5) Start address (6) First instruction ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset vector (H'0000) (2) Start address (contents of reset vector) (3) First instruction of program 4.2.3 Interrupts after Reset If ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ 30 internal sources in the on-chip supporting modules. Figure 4-5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Stack Status after Exception Handling Figure 4-6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area Before exception handling SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack ...
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Notes on Stack Usage When accessing word data or longword data, the H8/3042 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in ...
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Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . ADI ADIE Interrupt controller Legend ISCR: IRQ sense control register ...
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Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Nonmaskable interrupt External interrupt request IRQ 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 Initial value 0 Read/Write R/W Priority level A6 Selects the priority level of IRQ interrupt requests Priority level ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller interrupt requests. Bit 3 IPRA3 Description 0 WDT and refresh controller interrupt requests have priority level 0 (low priority) 1 WDT and refresh controller interrupt requests ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 Initial value 0 Read/Write R/W Priority level B7 Selects the priority level of ITU channel 3 interrupt requests ...
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Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7 IPRB7 Description 0 ITU channel 3 interrupt requests have priority level 0 (low priority) 1 ITU channel 3 interrupt requests have priority level ...
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Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description 0 SCI0 interrupt requests have priority level 0 (low priority) 1 SCI0 interrupt requests have priority level 1 (high priority) Bit ...
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IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 — Initial value 0 Read/Write — Reserved bits Note: Only 0 can be written, to clear flags. * ISR is ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 — Initial value 0 Read/Write R/W Reserved bits IER is initialized to H' reset and in hardware standby mode. Bits ...
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IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ 5 0 Bit 7 — Initial value 0 Read/Write R/W Reserved bits ISCR ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ IRQ can be used to exit software standby mode. 2 NMI: NMI is the highest-priority interrupt and is ...
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Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Note Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of ...
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Table 5-3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog 20 (interval timer) timer CMI Refresh (compare match) controller Reserved ...
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Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Interrupt Source Origin IMIA2 ITU (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — IMIA3 ITU (compare match channel 3 /input capture ...
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Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 ...
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Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3042 Series handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled by ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when ...
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If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- ...
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Figure 5-5 shows the transitions among the above states. a. All interrupts are unmasked I 0 Figure 5-5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when • ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Yes Yes Read vector address Figure 5-6 Process Up to Interrupt Acceptance when ...
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Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, ...
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Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time No. Item 1 Interrupt priority decision ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...
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Overview The H8/3042 Series has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. A bus arbitration function ...
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Block Diagram Figure 6-1 shows a block diagram of the bus controller. Internal address bus Area decoder WAIT Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus request signal CPU bus acknowledge signal DMAC bus ...
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Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write WAIT Wait ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 1 Mode Initial value 0 Mode ...
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Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit 7 AST7 Initial value 1 Read/Write R/W ASTCR is initialized to H' ...
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Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit 7 — Initial value 1 Read/Write — WCR is initialized to ...
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Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 WC1 WC0 Description wait states inserted by wait-state controller ...
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Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A and enables or disables release of the bus to an external device. Bit 7 A23E Initial value 1 — Mode ...
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Bit 5—Address 21 Enable (A21E): Enables PA Writing 0 in this bit enables A cannot be modified and PA 6 Bit 5 A21E Description the A address output pin the PA /TP ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general ...
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Chip select signals ( area can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ABWCR ASTCR WCER ABWn ASTn WCEn 0 0 — ...
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Chip Select Signals For each of areas the H8/3042 Series can output a chip select signal (CS low to indicate when the area is selected. Figure 6-3 shows the output timing ...
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Data Bus The H8/3042 Series allows either 8-bit access or 16-bit access to be designated for each of areas 8-bit-access area uses the upper data bus (D both the upper data bus ( ...
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Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper address bus (D pin is always high. Wait states can be inserted. ø Address bus CS ...
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Two-State-Access Areas: Figure 6-5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper address bus (D pin is always high. Wait states cannot be inserted. ø Address bus Read D 15 ...
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Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D can be inserted. ø Address ...
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Address bus Read access HWR LWR Write access Note (but ...
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Address bus Read access HWR LWR Write access Note (but ...
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Two-State-Access Areas: Figures 6-9 to 6-11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D cannot be inserted. ø Address ...
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Address bus Read access HWR LWR Write access Note (but ...
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Address bus Read access HWR LWR Write access Note (but ...
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Wait Modes Four wait modes can be selected for each area as shown in table 6-5. Table 6-5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 — — — ...
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Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by pin control. During access to an external three-state-access area, if the of the system clock (ø) in the T wait states continue to ...
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Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. If the W clock (ø) in the last of these wait states, an additional ...
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Pin Auto-Wait Mode: If the WC1 and WC0 are inserted. In pin auto-wait mode, if the the number of wait states (T W states are inserted even if the interface to low-speed memory, simply by routing the chip select signal ...
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Programmable Wait Mode: The number of wait states (T inserted in all accesses to external three-state-access areas. Figure 6-15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø Address bus AS RD Read ...
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Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying ...
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Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the ...
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H8/3042 Series WAIT RD HWR LWR Figure 6-18 Interconnections with Memory (Example ...
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Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has ...
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DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the bus arbiter transfers the ...
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Figure 6-19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until ...
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Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. 6.4.2 Register Write Timing ...
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DDR Write Timing: Data written to a data direction register (DDR) to change output to generic input, or vice versa, takes effect starting from the T n cycle. Figure 6-21 shows the timing when the CS output. ...
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BREQ 6.4.3 Input Timing BREQ After driving the pin low, hold it low until BACK level before goes low, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ If is high for too short an ...
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Section 7 Refresh Controller 7.1 Overview The H8/3042 Series has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address ...
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Features as an Interval Timer • Refresh timer counter (RTCNT) can be used as an 8-bit up-counter • Selection of seven counter clock sources: ø/2, ø/8, ø/32, ø/128, ø/512, ø/2048, ø/4096 • Interrupts can be generated by compare match between ...
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Input/Output Pins Table 7-1 summarizes the refresh controller’s input/output pins. Table 7-1 Refresh Controller Pins Signal Pin Name RFSH Refresh HWR Upper write/upper column address strobe LWR Lower write/lower column address strobe RD Column address strobe/ write enable CS ...
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Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit 7 SRFMD PSRAME Initial value 0 Read/Write R/W PSRAM enable and DRAM enable These bits enable ...
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Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3042/1/0 enters software ...
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Bit 4—Strobe Mode Select (CAS/ valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 4 CAS/WE Description 0 2WE mode 1 2CAS mode Bit 3—Address ...
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Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. Bit 7 CMF Initial ...
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Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit ...
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Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. Bit 7 Initial value 0 Read/Write R/W RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches ...
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Operation 7.3.1 Area Division One of three functions can be selected for the H8/3042 Series refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7-3 summarizes the ...
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Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will be requested at ...
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Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles Area 3 Settings Read/Write Cycle by CPU or DMAC 2-state-access area • 3 states (AST3 = 0) • Wait states cannot be inserted 3-state-access area • 3 states (AST3 ...
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Address Multiplexing: Address multiplexing depends on the setting of the M9/ RFSHCR, as described in table 7-5. Figure 7-4 shows the address output timing. Address output is multiplexed only in area 3. Table 7-5 Address Multiplexing Address Pins Address signals ...
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CAS WE 2 and 2 Modes: The CAS/ UCAS wide DRAM: one using correspond to H8/3042/1/0 pins as shown in table 7-6. Table 7-6 DRAM Pins and H8/3003 Pins H8/3042/1/0 Pin CAS/ (2WE mode) HWR UW LWR LW ...
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Read cycle ø Address Row Column bus CS 3 RAS ( ) HWR UCAS ( ) LWR LCAS ( ) RFSH AS Note: * 16-bit access Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode) ...
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Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set RFSHCR, when a transition to software standby mode occurs, the outputs go low in that order so that the DRAM self-refresh function ...
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Address bus CS (RAS (CAS) HWR (UW) High LWR (LW) High RFSH ø Address bus CS (RAS) 3 HWR (UCAS) LWR (LCAS) RD (WE) RFSH Figure 7-6 Signal Output Timing in Self-Refresh Mode (PSRAME = 0, DRAME ...
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Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits and RTCOR retain their settings prior to ...
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Set area 3 for 16-bit access Set P8 DDR to 1 for 1 Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-8 Setup Procedure for 2 ...
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Example 2: Connection to 2 interconnections to a single 2 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 10-bit row addresses and 8-bit column addresses. Its address area is ...
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Set P8 DDR to 1 for Set bits CKS2 to CKS0 in RTMCSR Figure 7-10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS output 1 ...
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Example 3: Connection to 2 interconnections to a single 2 Figure 7-12 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 9-bit row addresses and 9-bit column addresses. Its address ...
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Set P8 DDR to 1 for Set bits CKS2 to CKS0 in RTMCSR Figure 7-12 Setup Procedure for 2 9-Bit Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS output 1 3 Set RTCOR Write H'3B in RFSHCR ...
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Example 4: Connection to Two 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows an example of interconnections to two 2 map four DRAM chips can be connected to area 3 by decoding upper address bits A and A ...
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Set P8 DDR to 1 for CS output Set bits CKS2 to CKS0 in RTMCSR Wait for DRAM to be initialized Figure 7-14 Setup Procedure for Multiple 2CAS 4-Mbit DRAM Chips with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte ...
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Pseudo-Static RAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. The numbers of states required ...
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Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 ...
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Address bus High HWR LWR RFSH Figure 7-16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0) Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in ...
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Example: Pseudo-static RAM may have separate OE RFSH into a single / pin. Figure 7-17 shows an example of a circuit for generating an OE RFSH / signal. Check the device characteristics carefully, and design a circuit that fits them. ...
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Set P8 DDR to 1 for CS output 1 Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed Figure 7-18 Setup Procedure for Pseudo-Static RAM 172 ...
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Interval Timing To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to ...
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Contention between RTCNT Write and Counter Clear counter clear signal occurs in the T state of an RTCNT write cycle, clearing of the counter takes priority and the write is not 3 performed. See figure 7-20. ø Address ...
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Contention between RTCNT Write and Increment increment pulse occurs in the RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7-21. ø Address bus Internal write signal RTCNT input clock RTCNT ...
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Contention between RTCOR Write and Compare Match compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7-22. ø Address bus Internal write signal ...
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Table 7-9 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 No. Write Timing *1 1 Low low switchover 2 Low high switchover Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted ...
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Table 7-9 Internal Clock Switchover and RTCNT Operation (cont) CKS2 to CKS0 No. Write Timing 3 High low switchover 4 High high switchover Notes: 1. Including switchover from a high clock source to the halted state. 2. The switchover is ...
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Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. 7.5 Usage Notes When using the DRAM or ...
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If a bus cycle is prolonged by insertion of wait states, the first refresh request is held the bus-released state. • If contention occurs between a transition to software standby mode and a bus request from an ...
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Section 8 DMA Controller 8.1 Overview The H8/3042 Series has an on-chip DMA controller (DMAC) that can transfer data four channels. 8.1.1 Features DMAC features are listed below. • Selection of short address mode or full address ...
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Block Diagram Figure 8-1 shows a DMAC block diagram. Internal IMIA0 interrupts IMIA1 IMIA2 IMIA3 TXI0 RXI0 DREQ0 Control logic DREQ1 TEND0 TEND1 Interrupt DEND0A signals DEND0B DEND1A DEND1B Data buffer Legend DTCR: Data transfer control register MAR: Memory ...
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Functional Overview Table 8-1 gives an overview of the DMAC functions. Table 8-1 DMAC Functional Overview Transfer Mode Short I/O mode address • Transfers one byte or one word mode per request • Increments or decrements the memory address ...
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Input/Output Pins Table 8-2 lists the DMAC pins. Table 8-2 DMAC Pins Channel Name 0 DMA request 0 Transfer end 0 1 DMA request 1 Transfer end 1 Note: External requests cannot be made to channel A in short ...
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Table 8-3 DMAC Registers Channel Address* Name 0 H'FF20 Memory address register 0AR H'FF21 Memory address register 0AE H'FF22 Memory address register 0AH H'FF23 Memory address register 0AL H'FF26 I/O address register 0A H'FF24 Execute transfer count register 0AH H'FF25 ...
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Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as ...
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I/O Address Registers (IOAR) An I/O address register (IOAR 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all ...
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Repeat mode Bit 7 Initial value Read/Write R/W Bit 7 Initial value Read/Write R/W In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one ...