MS81V04160-25TB Oki Semiconductor, MS81V04160-25TB Datasheet
MS81V04160-25TB
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MS81V04160-25TB Summary of contents
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... The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory (MSM51V8222A), can be used as a x16 configuration FIFO. The MS81V04160 is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems ...
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... Access Time 22ns/25ns Variable length delay bit (600 to 262215) Write mask function (Output enable control) Cascading capability by mode setting p Single power supply:3.3V Package: 100-Pin plastic TQFP(TQFP 100-P-1414-0.50-k)(Product:MS81V04160-xxTB) Parameter Access Time Read/Write Cycle Time Operation current Standby current 10% xx indicates speed rank. ...
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... MS81V04160 PIN CONFIGURATION (TOP VIEW Vss Vss 10 Vss 11 Vcc 12 Vcc 13 SWCK 14 Vcc 15 Vcc 16 Vss 17 Vss Vss Function Pin Name Serial Write Clock ...
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... MS81V04160 BLOCK DIAGRAM OKI Semiconductor 4 ...
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... MS81V04160 PIN DESCRIPTION Data Inputs: (DIN 10 - 17) These pins are used for serial data inputs. Write Reset: RSTW1 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK. ...
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... MS81V04160 Serial Write Clock: SWCK The SWCK latches the input data on chip when WE1 high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Serial Read Clock: SRCK Data is shifted out of the data registers ...
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... MS81V04160 Output Enable: OE2 OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are referenced to the rising edge of SRCK. ...
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... MS81V04160 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Input Output Voltage V Output Current I Power Dissipation P T Operating Temperature Storage Temperature T Recommended Operating Conditions Parameter Symbol Power Supply Voltage V Power Supply Voltage V Input High Voltage V Input Low Voltage V DC Characteristics Parameter Symbol ...
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... RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) OKI Semiconductor ( Vcc = 3.0 - 3.6V, MS81V04160-25 MS81V04160-30 Symbol Min. Max. Min. Max ...
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... MS81V04160 Notes: 1. Input signal reference levels for the parameter measurement are The transition time t IL between V = 3.0 V and measurements assume t 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. ...
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... MS81V04160 OPERATION MODE Write Operation Cycle (MODE2=Vss) The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1, WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding WE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be preformed for internal circuit initialization before Write operation ...
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... MS81V04160 Settings of WE1, 2 and IE1 the operation mode of Write address pointer and Data input. WE1,2 IE1 Read Operation Cycle (MODE2=Vss) The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding both RE1 and OE1 high after the read address pointer reset operation or RSTR1 ...
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... MS81V04160 Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 us after Vcc has stabilized to a value within the range of recommended operating conditions. After this 100 us stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of ...
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... MS81V04160 TIMING WAVEFORM Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vss n cycle SWCK tRSTWS RSTW 1,2 tDS tDH DI n-1 10-17/20-27 IE 1,2 WE 1,2 Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vss n cycle SWCK tWENH tWWEL WE 1,2 DI n-1 10-17/20-27 IE 1,2 RSTW 1,2 0 cycle 1 cycle tRSTWH tWSWH tWSWL tSWC n 0 Disable cycle Disable cycle ...
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... MS81V04160 Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vss n cycle SWCK tIENH tWIEL IE 1,2 DI n-1 10-17/20-27 WE 1,2 RSTW 1,2 Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vcc n cycle SWCK tRSTWS RSTW 1,2 tDS tDH DI n-1 10-27/20-27 WE 1,2 IE 1,2 n+1 cycle n+2 cycle tIDSH tIENS tIDSS tWIEH n 0 cycle tRSTWH OKI Semiconductor n+3 cycle ...
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... MS81V04160 Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vcc n cycle SWCK tWENH tWWEL WE 1,2 DI n-1 10-17/20-27 IE 1,2 RSTW1,2 Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vcc n cycle SWCK tIENH tWIEL IE 1,2 DI n-1 10-17/20-27 WE 1,2 RSTW 1,2 Disable cycle Disable cycle tWDSH tWDSS tWENS tWWEH n n+1 cycle n+2 cycle tIDSH tIDSS tIENS tWIEH ...
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... MS81V04160 Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vss n cycle SWCK tRSTWS RSTW 1,2 tDS tDH DI n 10-17/20-27 WE 1,2 IE 1,2 Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vss n cycle SWCK tWENH tWWEL WE 1 10-17/20-27 IE 1,2 RSTW 1,2 0 cycle 1 cycle tRSTWH tWSWH tWSWL tSWC 0 1 Disable cycle Disable cycle ...
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... MS81V04160 Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vss n cycle SWCK tIENH tWIEL IE 1 10-17/20-27 WE 1,2 RSTW 1,2 Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vcc n cycle SWCK RSTW 1,2 tDS tDH DI n-1 10-27/20-27 WE 1,2 IE 1,2 n+1 cycle n+2 cycle tIDSH tIENS tIDSS tWIEH n n-1 cycle 0 cycle tRSTWS tRSTWH OKI Semiconductor ...
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... MS81V04160 Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vcc n cycle SWCK tWENH tWWEL WE 1 10-17/20-27 IE 1,2 RSTW1,2 Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vcc n cycle SWCK tIENH tWIEL IE 1 10-17/20-27 WE 1,2 RSTW 1,2 Disable cycle Disable cycle tWDSH tWDSS tWENS tWWEH n+1 n+1 cycle n+2 cycle tIDSH tIDSS ...
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... MS81V04160 Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vss n cycle SRCK tRSTRS RSTR 1,2 tAC DO n-1 10-17/20-27 RE 1,2 OE 1,2 Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vss n cycle SRCK tRENH tWREL RE 1,2 DO n-1 10-17/20-27 OE 1,2 RSTR 1,2 1 cycle 0 cycle tRSTRH tWSRH tWSRL tSRC tDDCK n 0 Disable cycle Disable cycle tRDSH tRDSS ...
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... MS81V04160 Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vss n cycle SRCK tOENH tWOEL OE 1,2 DO n-1 10-17/20-27 RE 1,2 RSTR 1,2 Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vcc n cycle SRCK tRSTRS RSTR 1,2 tAC DO n-1 10-17/20-27 RE 1,2 OE 1,2 n+1 cycle n+2 cycle tODSH tOENS tODSS tWOEH n Hi-Z 0 cycle 1 cycle tRSTRH OKI Semiconductor n+3 cycle ...
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... MS81V04160 Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vcc n cycle SRCK tRENH RE 1,2 tWREL tAC DO n-1 10-17/20-27 OE 1,2 RSTR 1,2 Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vcc n cycle SRCK tOENH OE 1,2 tWOEL DO n-1 10-17/20-27 RE 1,2 RSTR 1,2 Disable cycle Disable cycle tRDSH tRDSS tRENS tWREH n n+1 cycle n+2 cycle tODSH tODSS tOENS ...