MSM56V16160F-10TS-K Oki Semiconductor, MSM56V16160F-10TS-K Datasheet

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MSM56V16160F-10TS-K

Manufacturer Part Number
MSM56V16160F-10TS-K
Description
2-bank x 524,288-word x 16-bit cynchronous dynamic RAM
Manufacturer
Oki Semiconductor
Datasheet
MSM56V16160F
2-Bank ´ ´ ´ ´ 524,288 Word ´ ´ ´ ´ 16 Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16160F is a 2-Bank ´ 524,288-word ´ 16 bit Synchronous dynamic RAM, fabricated in OKI’s
CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL
compatible.
FEATURES
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PRODUCT FAMILY
MSM56V16160F-8
MSM56V16160F-10
50-pin 400mil plastic TSOP (Type II) (TSOPII50-P-400-0.80-K)
Silicon gate , quadruple polysilicon CMOS , 1-transistor memory cell
2-bank ´ 524,288-word ´ 16bit configuration
3.3V power supply ± 0.3V tolerance
Input
Output
Refresh
Programmable data transfer mode
CBR auto-refresh, Self-refresh capability
Package:
- CAS Latency (1,2,3)
- Burst Length (1,2,4,8,Full page)
- Data scramble (sequential , interleave)
Family
: LVTTL compatible
: LVTTL compatible
: 4096 cycles/64 ms
Semiconductor
Frequency
125MHz
100MHz
Max.
Access Time (Max.)
t
AC2
9ns
9ns
(Product : MSM56V16160F-xxTS-K)
t
AC3
6ns
9ns
This version : Sep.1999
xx : indicates speed rank.
1/30

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MSM56V16160F-10TS-K Summary of contents

Page 1

... Word ´ ´ ´ ´ 16 Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16160F is a 2-Bank ´ 524,288-word ´ 16 bit Synchronous dynamic RAM, fabricated in OKI’s CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible ...

Page 2

... Function Data Input/Output Mask DQi Data Input/Output V Power Supply (3.3V Ground (0V Data Output Power Supply (3.3V Data Output Ground (0V Connection pin and V CC pin and V Q pin MSM56V16160F Q pin. CC 2/30 ...

Page 3

... Masks the write data of the same clock when UDQM and LDQM are set “H” LDQM at the “H” edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. DQi Data inputs/outputs are multiplexed on the same pin. : RA0 – RA10 MSM56V16160F 3/30 ...

Page 4

... Word Decoders Drivers Row Row Word 12 Decoders Drivers Latency I/O & Burst Controller Controller Input Input Data Buffers Register 16 Column Decoders Sense 16 16 Amplifiers Read Output Data Buffers Register 8Mb Memory Cells 8Mb Memory Cells Sense Amplifiers Column Decoders MSM56V16160F 16 DQ1 16 - DQ16 4/30 ...

Page 5

... opr *: Ta = 25°C Symbol Min 2 Symbol C CLK C C OUT MSM56V16160F (Voltages referenced to V Rating -0 0.5 CC -0.5 to 4.6 -55 to 150 600 (Voltages referenced to V Typ. Max. 3.3 3.6 + 0.2 ¾ ¾ 0 1.4V 25° 1MHz) BIAS Min. Max. ...

Page 6

... CC IH Active t =min. One Bank CC CKE³V IH Active t =min. RC Both Banks CKE£V t =min Precharge Both Banks t =min. CKE£ Precharge MSM56V16160F MSM56V16160 F-8 F-10 Unit Note Min Max Min Max ¾ ¾ 2.4 2.4 V ¾ ¾ 0.4 0.4 V -10 - µA -10 - µ ...

Page 7

... Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. Burst Type Sequential Interleave MSM56V16160F Burst Length Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved 1 Full Page ...

Page 8

... RRD ¾ t REF t t +1CLK PDE SI ¾ CCD l 1 CKE l 2 DOZ l 0 DOD l 0 DWD MSM56V16160F MSM56V16160 F-10 Max. Min. Max. ¾ ¾ 10 ¾ ¾ 15 ¾ ¾ 30 ¾ ¾ ¾ ¾ ¾ 3 ¾ ¾ 3 ¾ ...

Page 9

... The access time is defined at 1.5V longer than 1ns, then the reference level for timing of input signals MSM56V16160 F-8 Symbol Min. Max ROH l 3 MRD l 2 OWD = 1ns. T Z=50W MSM56V16160F Note 1,2 F-10 Unit Note Min. Max. CL Cycle 3 Cycle 2 Cycle 50pF (External Load) and ...

Page 10

... UDQM, LDQM Row Active Read Command OHZ Row Active Precharge Command MSM56V16160F Write Command Precharge Command 18 19 10/30 ...

Page 11

... OLZ OWD WE UDQM, LDQM Row Active Read Command High CCD OHZ Write Command Precharge Command Read Command MSM56V16160F 11/30 ...

Page 12

... After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. ) after UDQM, LDQM entry. OHZ MSM56V16160F 12/30 ...

Page 13

... To assert row precharge before a burst write ends, wait t Input data during the precharge input cycle will be masked internally High OWD * * * * Note 1 Write Command Write Command WR MSM56V16160F Note 2 WR Precharge Command after the last write data input 13/30 ...

Page 14

... High A-Bank Precharge Start A-Bank Precharge Start A-Bank Precharge Start Auto Precharge MSM56V16160F ...

Page 15

... Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb1 Q Bb2 Q Bb3 Q Bb4 Row Active Read Command Row Active (B-Bank) (B-Bank) (A-Bank) Precharge Command Precharge Command (A-Bank Ac0 Q Ac1 Q Ac2 Q Ac3 Read Command (A-Bank) (B-Bank) MSM56V16160F 15/30 ...

Page 16

... High Bb0 D Bb1 D Bb2 D Bb3 Precharge Row Active Command (A-Bank) (A-Bank) Write Command Precharge Command (B-Bank) MSM56V16160F Ac0 D Ac1 Write Command (A-Bank) Precharge Command (B-Bank) (A-Bank 16/30 ...

Page 17

... Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Bd0 Q Bd1 Q Ae0 Q Ae1 (B-Bank) Read Command Read Command (B-Bank) (A-Bank Read Command Precharge Command (B-Bank) Read Command (A-Bank) MSM56V16160F ROH (A-Bank) 17/30 ...

Page 18

... Write Command (A-Bank High Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 D Bd0 Write Command Write Command (B-Bank) (A-Bank Write Command (B-Bank) Precharge Command (Both Bank) MSM56V16160F 18/30 ...

Page 19

... High Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Row Active Write Command (B-Bank) (B-Bank) Precharge Command (A-Bank) MSM56V16160F Ac0 Q Ac1 Q Ac2 Q Ac3 Read Command (A-Bank) Row Active (A-Bank) ...

Page 20

... RAS CAS C Aa0 ADDR A11 A10 DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 WE UDQM, LDQM Read Command (A-Bank High C Bb0 D Bb0 D Bb1 D Bb2 D Bb3 Write Command (B-Bank) MSM56V16160F Ac0 Q Ac0 Q Ac1 Q Ac2 Q Ac3 Read Command (A-Bank 20/30 ...

Page 21

... Note OHZ Note 2 CLOCK Read Command Suspension Read DQM MSM56V16160F Note 3 t OHZ Write Read DQM DQM Write ...

Page 22

... In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM and LDQM must be high at least 3 clocks prior to the write command Note Precharge Command Write Command MSM56V16160F 22/30 ...

Page 23

... High * * * * Note ROH ROH Precharge Command Note Note ROH MSM56V16160F 23/30 ...

Page 24

... UDQM, LDQM Read Command High Burst Stop Write Command Command MSM56V16160F Burst Stop Command 19 24/30 ...

Page 25

... Power-down Entry *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16160F enters power-down mode and maintains the mode while CKE is low release the circuit from power-down mode, CKE has to be set high for longer than t ...

Page 26

... Self Refresh Cycle CLK CKE RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM Self Refresh Entry Self Refresh Exit MSM56V16160F Row Active 26/30 ...

Page 27

... Mode Register Set Cycle CLK High CKE CS l MRD RAS CAS Key ADDR UDQM, LDQM MRS New Command · · · · Auto Refresh Cycle Auto Refresh MSM56V16160F High Auto Refresh 10 11 27/30 ...

Page 28

... NOP (Continue Burst to End and enter Row Precharge NOP (Continue Burst to End and enter Row Precharge ILLEGAL CA, A10 ILLEGAL ILLEGAL RA, A10 ILLEGAL ILLEGAL MSM56V16160F Action 28/30 ...

Page 29

... X X ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL NOP = No OPeration command and t to prevent bus contention. CCD WR MSM56V16160F Action RCD RCD 29/30 ...

Page 30

... MSM56V16160F ADDR Action X INVALID X Exit Self Refresh --> ABI X Exit Self Refresh --> ABI X ILLEGAL X ILLEGAL X ILLEGAL X NOP (Maintain Self Refresh) X INVALID X Exit Power Down --> ABI X Exit Power Down --> ABI X ILLEGAL ...

Page 31

NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...

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