MSM51V17805F-60TS-K Oki Semiconductor, MSM51V17805F-60TS-K Datasheet

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MSM51V17805F-60TS-K

Manufacturer Part Number
MSM51V17805F-60TS-K
Description
2,097,152-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
Manufacturer
Oki Semiconductor
Datasheet
DESCRIPTION
The MSM51V17805F is a 2,097,152-word × 8-bit dynamic RAM fabricated in Oki’s silicon-gate
CMOS technology. The MSM51V17805F achieves high integration, high-speed operation, and
low-power
polysilicon/double-layer metal CMOS process. The MSM51V17805F is available in a 28-pin plastic
TSOP.
FEATURES
·
·
·
·
·
·
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· Packages
PRODUCT FAMILY
OKI Semiconductor
MSM51V17805F
2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
Single 3.3V power supply, ±0.3V tolerance
Input
Output : LVTTL compatible, 3-state
Refresh : 2048 cycles/32ms
Fast page mode with EDO, read modify write capability
28-pin 400mil plastic TSOP
2,097,152-word × 8-bit configuration
MSM51V17805F
Family
: LVTTL compatible, low input capacitance
consumption
50ns
60ns
70ns
t
RAC
because
Access Time (Max.)
25ns
30ns
35ns
t
AA
(
TSOPII28-P-400-1.27-K
Oki
13ns
15ns
20ns
t
CAC
manufactures
13ns
15ns
20ns
t
OEA
)
Cycle Time
the
104ns
124ns
(Min.)
(Product : MSM51V17805F-xxTS-K)
xx indicates speed rank.
84ns
device
Operating
360mW
324mW
288mW
in
(Max.)
Power Dissipation
Issue Date: Aug. 16, 2002
a
FEDD51V17805F-02
quadruple-layer
Standby
1.8mW
(Max.)
1/17

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MSM51V17805F-60TS-K Summary of contents

Page 1

... OKI Semiconductor MSM51V17805F 2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V17805F is a 2,097,152-word × 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V17805F achieves high integration, high-speed operation, and low-power consumption because polysilicon/double-layer metal CMOS process. The MSM51V17805F is available in a 28-pin plastic TSOP ...

Page 2

... 28-Pin Plastic TSOP (K Type) Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3V) Ground (0V) No Connection pin, and the same GND voltage level must CC FEDD51V17805F-02 MSM51V17805F 2/17 ...

Page 3

... A0 – A9 Address Control Clock Counter 10 Row Row Address 11 Deco- Buffers ders 1 A10R Chip V Generator BB On Chip IV Generator I/O Controller 10 Column Decoders I/O Sense Amplifiers 8 Selector Word Memory Drivers Cells FEDD51V17805F-02 MSM51V17805F Output 8 8 Buffers DQ1 – Input 8 8 Buffers 8 3/17 ...

Page 4

... Ta = 25° MHz) Symbol Min. C — IN1 C — IN2 C — I/O FEDD51V17805F-02 MSM51V17805F Value Unit –0 °C –55 to 150 °C ( 70°C) Max ...

Page 5

...     100 , IL   100 = Min. for output open condition FEDD51V17805F-02 MSM51V17805F = 3.3V ± 0.3V 70° MSM51V17805 F-60 F-70 Unit Note Max. Min. Max 0.4 0 0.4 V − 10 µ − 10 µ  ...

Page 6

... RASP  RSH  ROH  10,000 10 CAS  CSH FEDD51V17805F-02 MSM51V17805F MSM51V17805 F-70 Unit Note Max. Min. Max.   124 ns   160 ns       ...

Page 7

... DH  OED  CWD  AWD  RWD  CPWD FEDD51V17805F-02 MSM51V17805F MSM51V17805 F-70 Unit Note Max. Min. Max.        ...

Page 8

... CSR  CHR  WRP  WRH  WTS  WTH FEDD51V17805F-02 MSM51V17805F MSM51V17805 F-70 Unit Note Max. Min. Max.            ...

Page 9

... They are included in the data CPWD ≥ t (Min.), then the cycle is an early write cycle and WCS WCS ≥ t ≥ t (Min.) and t AWD AWD CPWD CPWD FEDD51V17805F-02 MSM51V17805F T (Max.) limit, RCD (Max.) limit, RAD ≥ t CWD CWD (Min.), then the cycle is a read modify 9/17 ) ...

Page 10

... Valid Data-out RAS t CSH t t RCD RSH t CAS t RAL t CAH t ASC Column t CWL t WCH RWL Valid Data-in FEDD51V17805F-02 MSM51V17805F CRP t RRH t RCH t REZ t CEZ t OEZ “H” or “L” CRP Open “H” or “L” 10/17 ...

Page 11

... RWC t RAS t CSH t t RCD RSH t CAS t t ASC CAH Column t t CWD RCS t RWD t AWD OEA t OED t CAC RAC t OEZ t CLZ Valid Data-out FEDD51V17805F-02 MSM51V17805F CRP t CWL t RWL OEH t DH Valid Data-in “H” or “L” 11/17 ...

Page 12

... ASC CAH CAH t ASC Column Column t RCS RCH t WPE OEA CAC WEZ CAC Valid Data-out t CLZ FEDD51V17805F-02 MSM51V17805F RHCP CAS t t ASC CAH CAH Column t t OCH RRH t t CAC CHO t OEP OEP t OEA t ...

Page 13

... OEA t t OED OEH CAC OEZ DH CAC Valid Valid Data-out Data- CLZ CLZ FEDD51V17805F-02 MSM51V17805F HPC RSH t CAS t t ASC CAH Column t t WCS WCH Valid Data-in “H” or “L” t ...

Page 14

... RAS RAH Open Note: WE “H” or “L” t RAS t CSR t CHR t t WRP WRH Open Note: OE, Address = “H” or “L” FEDD51V17805F-02 MSM51V17805F RPC “H” or “L” RPC t WRP “H” or “L” 14/17 ...

Page 15

... RAS t t RCD RSH RP t CAH t ASC Column t RAL t RWL WCH WRP Valid Data-in FEDD51V17805F-02 MSM51V17805F RAS CHR t REZ t t WRH CEZ t OEZ “H” or “L” RAS CHR t WRH “H” or “L” ...

Page 16

... Semiconductor REVISION HISTORY Document Date No. FEDD51V17805F-01 Dec, 2000 FEDD51V17805F-02 Aug, 2002 Page Previous Current Edition Edition – – Final edition Deleted SOJ package FEDD51V17805F-02 MSM51V17805F Description 16/17 ...

Page 17

... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDD51V17805F-02 MSM51V17805F Copyright 2002 Oki Electric Industry Co., Ltd. 17/17 ...

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