AM49PDL640AG70N Meet Spansion Inc., AM49PDL640AG70N Datasheet
AM49PDL640AG70N
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AM49PDL640AG70N Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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PRELIMINARY Am49PDL640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit ( 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage ...
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GENERAL DESCRIPTION Am29PDL640G Features The Am29PDL640G Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 73-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Figure 20. Back-to-back Read/Write Cycle Timings ....................... 51 Figure 21. Data# Polling Timings (During Embedded Algorithms).. 51 Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 52 Figure 23. DQ2 vs. DQ6.................................................................. 52 Temporary Sector Unprotect .................................................. 53 Figure 24. Temporary ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time (ns) t ACC Max Page Access (ns) t PACC CE#f Access (ns OE# Access (ns MCP BLOCK DIAGRAM ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & COMMAND CE# REGISTER WP#/ACC DQ15–DQ0 A21–A0 Mux PSRAM BLOCK DIAGRAM Refresh Control Refresh Counter Address A19-A0 Buffer DQ7-DQ0 DQ15-DQ8 ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A19– Address Inputs (Common) A21–A20 = 2 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#1s = Chip Enable 1 (pSRAM) CE2s = Chip Enable 2 (pSRAM) OE# = Output ...
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... Pseudo SRAM DEVICE DENSITY Mbits Order Number Am49PDL640AG70N Am49PDL640AG85N Am49PDL640AGa70N Am29PDL640AGa85N needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s (Notes 1, 2) (Note 7) H Read from Active L Flash (Note 8) H (Note 7) H Write to Active L Flash (Note 8) H ± V ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins control and selects the device. OE# is the output con- trol and gates array data to ...
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The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase op- eration the DC Characteristics table represents the ac- CC2 tive current specification for ...
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Output Disable Mode When the OE# input output from the device is IH disabled. The output pins (except for RY/BY#) are placed in the high impedance state. Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector ...
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Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector Address Size A21–A12 (Kwords) SA71 1000000xxx 32 SA72 1000001xxx 32 SA73 1000010xxx 32 SA74 1000011xxx 32 SA75 1000100xxx 32 SA76 1000101xxx 32 SA77 1000110xxx 32 SA78 1000111xxx 32 SA79 1001000xxx 32 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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SECTOR PROTECTION The Am29PDL640G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled ...
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This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared ...
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When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is ...
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If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin During this mode, formerly protected ID sectors can ...
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Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious ...
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Addresses Data 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses Data 1Bh 0027h 1Ch 0031h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 0009h ...
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Addresses Data 27h 0017h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0003h 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 007Dh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h 0000h 37h 0020h 38h 0000h 39h 0000h ...
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Table 12. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0004h 46h 0002h 47h 0001h 48h 0001h 49h 0007h 4Ah 0077h 4Bh 0000h 4Ch 0002h 4Dh 0085h 4Eh 0095h 4Fh 0001h ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 14 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...
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Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase ...
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The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. ...
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There are no pro- visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. There is no special addressing order required for pro- gramming the password. Also, when ...
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Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered ...
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Command Definitions Tables Table 13. Memory Array Command Definitions Command (Notes) Read (5) 1 Reset (6) 1 Manufacturer ID 4 Device ID (10) 6 Autoselect SecSi Sector Factory 4 (Note 7) Protect (8) Sector Group Protect 4 Verify (9) Program ...
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Table 14. Sector Protection Command Definitions Command (Notes) Reset 1 SecSi Sector Entry 3 SecSi Sector Exit 4 SecSi Protection Bit Program ( SecSi Protection Bit Status 4 Password Program ( Password Verify (8, 9) ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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PSRAM POWER DOWN CE2 = V IH Initial State Power (Wait 200 µs) Up Power Up Sequence Note:For Si-7 pSRAM, Deep Power-Down Standby is not available. Power Mode Standby Deep Power Down November 20, 2003 ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55 ° +125 ° C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current Active Read Current (Notes 1, 2) CC1 Active Write Current (Notes ...
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DC AND OPERATING CHARACTERISTICS (NOTE 1) Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO Operating Current at Minimum I s CC1 Cycle Time Operating Current at Maximum I s CC2 Cycle Time V ...
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TEST CONDITIONS Device Under Test C 6.2 k Ω L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input ...
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AC CHARACTERISTICS pSRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE# CE2# Figure 13. Timing Diagram for Alternating Test Setup — t CCR ...
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AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC ...
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AC CHARACTERISTICS A21-A3 A2-A0 Data CE# or CE2# OE Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Operation Timings Am49PDL640AG ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width ...
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AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: 1. SADD = sector address (for Sector ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 20. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, ...
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FLASH AC CHARACTERISTICS Flash Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS Power Up Time (Etron pSRAM only CE2s CE#1s V Slew Rate (Etron pSRAM only) CCS V CCS 0 Notes any time during Power Up, the V CCS 17 µ s/V). 2. Power ...
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Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Access Time BA t Chip ...
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AC CHARACTERISTICS Read Cycle Read Cycle 1-Addressed Controlled Address Previous Data Valid Data Out Note: 1. CE1 CE2 = WE Figure 29. pSRAM Read Cycle–Address Controlled Addr ess CE1# UB#, LB# ...
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AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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AC CHARACTERISTICS Addr ess CE#1s UB#, LB# WE# High-Z Data In Data Out Data Undefined Note: 1. CE2s = CE2s = WE Figure 31. pSRAM Write Cycle–WE# Controlled Addr ess CE#1s UB#, LB# ...
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PSRAM AC CHARACTERISTICS Addr ess CE#1s UB#, LB# WE# Data In High-Z Data Out Note: 1. CE2s = CE2s = WE Figure 33. pSRAM Write Cycle–UB#, LB# Controlled CE2s Normal Operation Mode CE#1s 62 ...
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PSRAM AC CHARACTERISTICS CE1 Address Note:Applies to Etron pSRAM only. CE1# WE# Address Note:Applies to Etron pSRAM only. CE1# WE# Address Note:Applies to Etron pSRAM only. November 20, 2003 ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25 ° ...
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PHYSICAL DIMENSIONS FLK073—73-Ball Fine-Pitch Grid Array 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 73X 0. 0. PACKAGE FLK ...
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REVISION SUMMARY Revision A (February 21, 2003) Initial Release Revision A+1 (March 14, 2003) Ordering Information Corrected typo in temperature range. Revision A+2 (April 4, 2003) Ordering Information Corrected typo in temperature range. Corrected OPNs Revision A+3 (April 7, 2003) ...
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