SST39SF020A-70-4C-PH Silicon Storage Technology, Inc, SST39SF020A-70-4C-PH Datasheet

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SST39SF020A-70-4C-PH

Manufacturer Part Number
SST39SF020A-70-4C-PH
Description
Multi-purpose flash
Manufacturer
Silicon Storage Technology, Inc
Datasheet

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FEATURES:
• Organized as 128K x8 / 256K x8 / 512K x8
• Single 5.0V Read and Write Operations
• Superior Reliability
• Low Power Consumption:
• Sector-Erase Capability
• Fast Read Access Time:
• Latched Address and Data
PRODUCT DESCRIPTION
The SST39SF010A/020A/040 are CMOS Multi-Purpose
Flash (MPF) manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39SF010A/020A/040 devices write
(Program or Erase) with a 5.0V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC stan-
dard pinouts for x8 memories.
Featuring
SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µsec. These devices use Toggle
Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they have
on-chip hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF010A/020A/040 devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a
©2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
1
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Active Current: 10 mA (typical)
– Standby Current: 30 µA (typical)
– Uniform 4 KByte sectors
– 45 and 70 ns
1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
high
performance
SST39SF010A / SST39SF020A / SST39SF040
398
SST39SF010A / 020A / 0405.0V 4Mb (x8) MPF memories
Byte-Program,
the
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
• Fast Erase and Byte-Program:
• Automatic Write Timing
• End-of-Write Detection
• TTL I/O Compatibility
• JEDEC Standard
• Packages Available
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF010A/020A/040 are offered in 32-pin PLCC and
32-pin TSOP packages. A 600 mil, 32-pin PDIP is also
available. See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
– Internal V
– Toggle Bit
– Data# Polling
– Flash EEPROM Pinouts and command sets
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP
2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040
PP
Generation
These specifications are subject to change without notice.
MPF is a trademark of Silicon Storage Technology, Inc.
Preliminary Specification

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SST39SF020A-70-4C-PH Summary of contents

Page 1

... Fast Erase and Byte-Program: – Sector-Erase Time (typical) – Chip-Erase Time (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040 • Automatic Write Timing – Internal V Generation PP • ...

Page 2

... Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector- Erase operation will be ignored. ...

Page 3

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification tor- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit ( During the internal Program or Erase operation, any con- ...

Page 4

... DQ0 DQ0 FIGURE SSIGNMENTS FOR ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 X-Decoder Control Logic SST39SF010A 32-pin PLCC ...

Page 5

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification SST39SF040 SST39SF020A SST39SF010A A11 A11 A11 A13 A13 A13 A14 A14 A14 A17 A17 NC WE# WE# WE A18 NC NC A16 A16 A16 A15 A15 A15 A12 ...

Page 6

... Erase Standby Write Inhibit Product Identification Software Mode 1. X can but no other value ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 -A address lines will select the sector for SST39SF040 18 CE# OE# WE ...

Page 7

... SST Manufacturer’s ID= BFH, is read with SST39SF010A Device ID = B5H, is read with A SST39SF020A Device ID = B6H, is read with A SST39SF040 Device ID = B7H, is read with A 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” ...

Page 8

... Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 V = 5.0V±10% DD Limits Min Max Units Test Conditions ...

Page 9

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification AC CHARACTERISTICS TABLE EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output ...

Page 10

... ADDRESS A MS-0 CE# OE WE# HIGH-Z DQ 7-0 Note Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE EAD YCLE IMING 5555 ADDRESS OE# CE# DQ 7-0 AA SW0 Note Most significant address ...

Page 11

... for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 6: CE# C ONTROLLED ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE ATA OLLING IMING ©2001 Silicon Storage Technology, Inc. INTERNAL PROGRAM OPERATION STARTS ...

Page 12

... ADDRESS A MS-0 CE# OE# WE Note: Toggle bit output is always high first Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE OGGLE IT IMING 5555 ADDRESS A MS-0 CE# OE WE# DQ 7-0 AA SW0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met ...

Page 13

... Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10 Sector Address Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 10: WE# C ONTROLLED Three-byte sequence for ...

Page 14

... ADDRESS A 14-0 DQ 7-0 AA CE# OE WE# SW0 FIGURE 12 OFTWARE XIT AND ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 IDA T WHP SW1 SW2 R ESET 14 Preliminary Specification 398 ILL F10.0 S71147-02-000 5/01 398 ...

Page 15

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification V IHT INPUT V ILT AC test inputs are driven at V (3.0V) for a logic “1” and V IHT and outputs are V (1.5V) and FIGURE 13 NPUT UTPUT TO DUT FIGURE 14 EST OAD XAMPLE © ...

Page 16

... FIGURE 15 YTE ROGRAM LGORITHM ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of ...

Page 17

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification Internal Timer Byte Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 16 AIT PTIONS ©2001 Silicon Storage Technology, Inc. Toggle Bit Byte Program/Erase Initiated Read byte Read same No byte No Does DQ 6 ...

Page 18

... Wait T IDA Read Software ID FIGURE 17 OFTWARE RODUCT ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: F0H ...

Page 19

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification Chip-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H ...

Page 20

... U = Unencapsulated die Temperature Range C = Commercial = 0°C to +70° Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed Version Device Density 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage S = 5.0±10%V SST39SF040-70-4C-PH SST39SF010A-70-4C-PH SST39SF020A-70-4C-PH 20 Preliminary Specification S71147-02-000 5/01 398 ...

Page 21

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification PACKAGING DIAGRAMS TOP VIEW .485 .495 .447 Optional .453 Pin #1 Identifier .042 .048 .042 .048 .585 .547 .595 .553 .050 BSC. Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...

Page 22

... SST ACKAGE ODE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1.645 1.655 .170 .200 .120 .150 .016 ...

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