SST39VF080-70-4C-EIE Silicon Storage Technology, Inc, SST39VF080-70-4C-EIE Datasheet

no-image

SST39VF080-70-4C-EIE

Manufacturer Part Number
SST39VF080-70-4C-EIE
Description
Manufacturer
Silicon Storage Technology, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST39VF080-70-4C-EIE
Manufacturer:
SST
Quantity:
5 530
Part Number:
SST39VF080-70-4C-EIE
Manufacturer:
SST
Quantity:
5 120
Part Number:
SST39VF080-70-4C-EIE
Manufacturer:
SST
Quantity:
73
Part Number:
SST39VF080-70-4C-EIE
Manufacturer:
SST
Quantity:
150
Part Number:
SST39VF080-70-4C-EIE
Manufacturer:
SST
Quantity:
1 904
Part Number:
SST39VF080-70-4C-EIE TSOP40
Manufacturer:
SST
Quantity:
1 011
FEATURES:
• Organized as 1M x8
• Single Voltage Read and Write Operations
• Superior Reliability
• Low Power Consumption
• Sector-Erase Capability
• Block-Erase Capability
• Fast Read Access Time:
PRODUCT DESCRIPTION
The SST39LF/VF080 devices are 1M x8 CMOS Multi-Pur-
pose Flash (MPF) manufactured with SST’s proprietary,
high-performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF080 write (Program or
Erase) with a 3.0-3.6V power supply. The SST39VF080
write (Program or Erase) with a 2.7-3.6V power supply.
They conform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39LF/
VF080 devices provide a typical Byte-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to indi-
cate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39LF/VF080 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
1
– 3.0-3.6V for SST39LF080
– 2.7-3.6V for SST39VF080
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
(typical values at 14 MHz)
– Active Current: 12 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
– Uniform 4 KByte sectors
– Uniform 64 KByte blocks
– 55 ns for SST39LF080
– 70 and 90 ns for SST39VF080
6/07
8 Mbit (x8) Multi-Purpose Flash
SST39LF/VF0803.0 & 2.7V 8Mb (x8) MPF memories
SST39LF080 / SST39VF080
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
• Latched Address and Data
• Fast Erase and Byte-Program:
• Automatic Write Timing
• End-of-Write Detection
• CMOS I/O Compatibility
• JEDEC Standard
• Packages Available
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. They also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39LF/VF080 are offered in 40-lead TSOP and 48-
ball TFBGA packages. See Figures 1 and 2 for pin
assignments.
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
– Internal V
– Toggle Bit
– Data# Polling
– Flash EEPROM Pinouts and command sets
– 40-lead TSOP (10mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
15 seconds (typical) for SST39LF/VF080
PP
Generation
These specifications are subject to change without notice.
MPF is a trademark of Silicon Storage Technology, Inc.
EOL Data Sheet

Related parts for SST39VF080-70-4C-EIE

SST39VF080-70-4C-EIE Summary of contents

Page 1

... The SST39LF080 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080 write (Program or Erase) with a 2.7-3.6V power supply. They conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF/ VF080 devices provide a typical Byte-Program time of 14 µ ...

Page 2

... During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program ©2007 Silicon Storage Technology, Inc. 8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. ...

Page 3

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- ...

Page 4

... EOL Data Sheet Product Identification The Product Identification mode identifies the device as SST39LF080 or SST39VF080 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification opera- tion to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see ...

Page 5

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 A16 A15 A14 A13 A12 A11 A18 FIGURE 1: Pin Assignments for 40-lead TSOP FIGURE 2: Pin Assignments for 48-ball TFBGA ©2007 Silicon Storage Technology, Inc Standard Pinout ...

Page 6

... X X High High OUT High OUT Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 -A address lines will select the MS 12 T2.4 1146 Address Sector or Block address, XXH for Chip-Erase See Table 4 T3.4 1146 S71146-07-EOL 6/07 ...

Page 7

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 TABLE OFTWARE OMMAND Command 1st Bus Sequence Write Cycle 1 Addr Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Block-Erase 5555H AAH Chip-Erase 5555H AAH 4,5 Software ID Entry 5555H AAH 4 CFI Query Entry 5555H AAH 6 Software ID Exit / XXH ...

Page 8

... Maximum time out for buffer program 2 25H 01H Maximum time out for individual Sector/Block-Erase 2 26H 01H Maximum time out for Chip-Erase 2 1. 0030H for SST39LF080 and 0027H for SST39VF080 TABLE EVICE EOMETRY NFORMATION FOR Address Data Data ...

Page 9

... Industrial -40°C to +85° ONDITIONS OF EST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . C Output Load . . . . . . . . . . . . . . . . . . . . C See Figures 14 and 15 ©2007 Silicon Storage Technology, Inc 3.0-3. 2.7-3.6V 2.7-3. for SST39LF080 L = 100 pF for SST39VF080 L 9 EOL Data Sheet +0.5V DD +2.0V DD S71146-07-EOL 6/07 ...

Page 10

... V 0 OWER UP IMINGS Minimum Specification 10,000 100 100 + Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 1 Test Conditions Address input f=1/T Min ILT IHT Max DD DD CE#=V , OE#=WE#=V , all I/Os open IL IH CE#=WE#=V , OE#= CE#= Max IHC DD DD CE#= ...

Page 11

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 AC CHARACTERISTICS TABLE 12 EAD YCLE IMING V = 3.0-3.6V SST39LF080 FOR DD Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output CLZ 1 T OE# Low to Active Output ...

Page 12

... T CLZ DATA VALID 2AAA 5555 ADDR WPH DATA SW1 SW2 BYTE (ADDR/DATA Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 OHZ T CHZ T OH HIGH-Z DATA VALID INTERNAL PROGRAM OPERATION STARTS 1146 F03.2 S71146-07-EOL 1146 F02.2 6/07 ...

Page 13

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 5555 ADDRESS OE# WE 7-0 SW0 FIGURE 5: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# WE# DATA DQ 7 FIGURE 6: Data# Polling Timing Diagram ©2007 Silicon Storage Technology, Inc. 2AAA 5555 ADDR CPH ...

Page 14

... Silicon Storage Technology, Inc OEH SIX-BYTE CODE FOR CHIP-ERASE 2AAA 5555 5555 2AAA SW1 SW2 SW3 SW4 14 8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 T OES TWO READ CYCLES WITH SAME OUTPUTS 1146 F06.2 T SCE 5555 10 SW5 1146 F08.3 S71146-07-EOL 6/07 ...

Page 15

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 5555 ADDRESS A MS-0 CE 7-0 SW0 FIGURE 9: WE# Controlled Block-Erase Timing Diagram 5555 ADDRESS A MS-0 CE 7-0 SW0 FIGURE 10: WE# Controlled Sector-Erase Timing Diagram ©2007 Silicon Storage Technology, Inc. SIX-BYTE CODE FOR BLOCK-ERASE 2AAA ...

Page 16

... SW0 FIGURE 12: CFI Query Entry and Read ©2007 Silicon Storage Technology, Inc. 5555 0000 T IDA T WPH SW1 SW2 5555 T IDA T WPH SW1 SW2 16 8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 0001 Device ID 1146 F11.4 1146 F12.0 S71146-07-EOL 6/07 ...

Page 17

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A 14-0 DQ 7-0 AA CE# OE WE# SW0 FIGURE 13: Software ID Exit/CFI Exit ©2007 Silicon Storage Technology, Inc. 2AAA 5555 IDA T WHP SW1 SW2 17 EOL Data Sheet 1146 F13.0 S71146-07-EOL ...

Page 18

... V (0 ILT DD ) and V (0 Input rise and fall times (10 TESTER 1146 F15 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 V OT OUTPUT 1146 F14.1 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test IT INPUT ...

Page 19

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 FIGURE 16: Byte-Program Algorithm ©2007 Silicon Storage Technology, Inc. Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling bit, or Toggle bit ...

Page 20

... EOL Data Sheet Internal Timer Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 17: Wait Options ©2007 Silicon Storage Technology, Inc. 8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 Toggle Bit Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase ...

Page 21

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 CFI Query Entry Software Product ID Entry Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 98H Address: 5555H Wait T IDA Read CFI data FIGURE 18: Software ID/CFI Command Flowcharts ©2007 Silicon Storage Technology, Inc. ...

Page 22

... Load data: 10H Address: 5555H Wait T SCE Chip erased to FFH FIGURE 19: Erase Command Sequence ©2007 Silicon Storage Technology, Inc. 8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 Sector-Erase Command Sequence Command Sequence Load data: AAH Load data: AAH Address: 5555H Address: 5555H Load data: 55H ...

Page 23

... XX XX XXXX - XXX Valid combinations for SST39LF080 SST39LF080-55-4C-EI SST39LF080-55-4C-B3K SST39LF080-55-4C-EIE SST39LF080-55-4C-B3KE Valid combinations for SST39VF080 SST39VF080-70-4C-EI SST39VF080-70-4C-B3K SST39VF080-70-4C-EIE SST39VF080-70-4C-B3KE SST39VF080-90-4C-EI SST39VF080-90-4C-B3K SST39VF080-90-4C-EIE SST39VF080-90-4C-B3KE SST39VF080-70-4I-EI SST39VF080-70-4I-B3K SST39VF080-70-4I-EIE SST39VF080-70-4I-B3KE SST39VF080-90-4I-EI SST39VF080-90-4I-B3K ...

Page 24

... All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. FIGURE 20: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm SST Package Code: EI ©2007 Silicon Storage Technology, Inc. 18.50 18.30 20.20 19. Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 1.05 0.95 0.50 BSC 0.27 10.10 0.17 9.90 0.15 0.05 DETAIL 1 ...

Page 25

... Mbit Multi-Purpose Flash SST39LF080 / SST39VF080 TOP VIEW 8.00 ± 0. CORNER SIDE VIEW SEATING PLANE Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0. Ball opening size is 0.38 mm (± 0.05 mm) ...

Related keywords