SST28SF040 Silicon Storage Technology, SST28SF040 Datasheet

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SST28SF040

Manufacturer Part Number
SST28SF040
Description
Manufacturer
Silicon Storage Technology
Datasheet

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FEATURES:
• Single Voltage Read and Write Operations
• Superior Reliability
• Memory Organization: 512K x 8
• Sector Erase Capability: 256 bytes per Sector
• Low Power Consumption
• Fast Sector Erase/Byte Program Operation
PRODUCT DESCRIPTION
The SST28SF040/28LF040/28VF040 are 512K x 8 bit
CMOS sector erase, byte program EEPROMs. The
SST28SF040/28LF040/28VF040 are manufactured us-
ing SST’s proprietary, high performance CMOS
SuperFlash EEPROM Technology. The split-gate cell
design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alterna-
tive approaches. The SST28SF040/28LF040/28VF040
erase and program with a single power supply. The
SST28SF040/28LF040/28VF040 conform to JEDEC
standard pinouts for byte wide memories and are com-
patible with existing industry standard EPROM, and
flash EEPROM pinouts.
Featuring high performance programming, the
SST28SF040/28LF040/28VF040 typically byte program
in 35 µs. The SST28SF040/28LF040/28VF040 typically
sector erase in 2 ms. Both program and erase times can
be optimized using interface features such as Toggle bit
or Data# Polling to indicate the completion of the write
cycle. To protect against an inadvertent write, the
SST28SF040/28LF040/28VF040 have on chip hard-
ware and software data protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, the SST28SF040/28LF040/28VF040 are offered
with a guaranteed sector endurance of 10
Data retention is rated greater than 100 years.
© 1999 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
309-02 1/99
– 5.0V-only for the SST28SF040
– 3.0-3.6V for the SST28LF040
– 2.7-3.6V for the SST28VF040
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Active Current: 15 mA (typical) for 5.0V and
– Standby Current: 5 µA (typical)
– Byte Program Time: 35 µs (typical)
– Sector Erase Time: 2 ms (typical)
– Complete Memory Rewrite: 20 sec (typical)
10 mA (typical) for 3.0-3.6V/2.7-3.6V
4 Megabit (512K x 8) SuperFlash EEPROM
SST28SF040 / SST28LF040 / SST28VF040
4
or 10
3
cycles.
1
• Fast Read Access Time
• Latched Address and Data
• Hardware and Software Data Protection
• End of Write Detection
• TTL I/O Compatibility
• JEDEC Standard
• Packages Available
The SST28SF040/28LF040/28VF040 are best suited for
applications that require reprogrammable nonvolatile
mass storage of program, configuration, or data
memory. For all system applications, the SST28SF040/
28LF040/28VF040 significantly improve performance
and reliability, while lowering power consumption when
compared with floppy diskettes or EPROM approaches.
EEPROM technology makes possible convenient and
economical updating of codes and control programs on-
line. The SST28SF040/28LF040/28VF040 improve flex-
ibility, while lowering the cost of program and configura-
tion storage application.
The functional block diagram shows the functional
blocks of the SST28SF040/28LF040/28VF040. Figures
1 and 2 show the pin assignments for the 32 pin TSOP,
32 pin PDIP, and 32 pin PLCC packages. Pin description
and operation modes are described in Tables 1
through 4.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first. Note, during the software data
protection sequence the addresses are latched on the
rising edge of OE# or CE#, whichever occurs first.
– 5.0V-only operation: 120 and 150 ns
– 3.0-3.6V operation: 200 and 250 ns
– 2.7-3.6V operation: 250 and 300 ns
– 7-Read-Cycle-Sequence Software Data
– Toggle Bit
– Data# Polling
– 32-Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 20mm)
Protection
– Flash EEPROM Pinouts
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

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SST28SF040 Summary of contents

Page 1

... TSOP (8mm x 20mm) The SST28SF040/28LF040/28VF040 are best suited for applications that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. For all system applications, the SST28SF040/ 28LF040/28VF040 significantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. ...

Page 2

... A sector contains 256 bytes. This sector erasability enhances the flexibility and usefulness of the SST28SF040/28LF040/28VF040, since most ap- plications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 20H to the device ...

Page 3

... Read mode and is Software Data pro- tected. The device must be unprotected to execute a Write command. The Read operation of the SST28SF040/28LF040/ 28VF040 are controlled by OE# and CE# at logic low. When high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins ...

Page 4

... SST. This mode may be accessed by hardware and software operations. The hardware operation is typically used by an external programmer to identify the correct algorithm for the SST28SF040/28LF040/28VF040. Us- ers may wish to use the software operation to identify the device (i.e., using the device code). For details see Table 2 for the hardware operation and Figure 18 for the software operation ...

Page 5

... Data is internally latched during a write cycle. The outputs are in tri-state when OE high. To activate the device when low. To gate the data output buffers. To control the write operations. To provide 5-volt supply (± 10%) for the SST28SF040, 3.0-3.6V supply for the SST28LF040 and 2.7-3.6V supply for the SST28VF040 5 32 OE# ...

Page 6

... Address 0000H retrieves the manufacturer’ code of BFH and address 0001H retrieves the device code of 04H ABLE EMORY RRAY ETAIL Sector Select Byte Select © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 OE# WE OUT ...

Page 7

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. ...

Page 8

... Output Low Voltage OL V Output High Voltage OH V Supervoltage for Supervoltage Current H for A 9 © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 C HARACTERISTICS Limits Min Max Units Test Conditions CE# = OE# =V all I/Os open 25 mA Address input = ...

Page 9

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 ABLE ECOMMENDED YSTEM OWER Symbol Parameter (1) T Power-up to Read Operation PU-READ (1) T Power-up to Write Operation PU-WRITE °C, f=1 MHz, other pins open) ABLE APACITANCE a Parameter Description (1) C I/O Pin Capacitance I/O (1) C Input Capacitance ...

Page 10

... CE# High to High-Z Output CHZ (1) tGLQX T OE# High to High-Z Output OHZ (1) tAXQX T Output Hold from Address OH Change © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 T P IMING ARAMETERS SST28SF040-120 SST28SF040-150 T P IMING ARAMETERS SST28LF040-200 SST28LF040-250 Min Max 200 200 ...

Page 11

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 T 13: SST28SF040 E /P ABLE RASE ROGRAM IEEE Industry Symbol Symbol tAVA T BP tWLWH T WP tAVWL T AS tWLAX T AH tELWL T CS tWHEX T CH tGHWL T OES tWGL T OEH tWLEH T CP tDVWH T DS tWHDX T DH tWHWL2 T SE (1) T RST ...

Page 12

... PCH (1) T PAS (1) T PAH (1) Note: This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 / RASE ROGRAM YCLE IMING ARAMETERS Parameter ...

Page 13

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 ADDRESS A 18-0 CE# OE# WE IGURE EAD YCLE IMING IAGRAM ADDRESS A 18-0 CE# OE# WE# DQ 7-0 I0H BYTE PROGRAM SETUP COMMAND IGURE ONTROLLED YTE © 1999 Silicon Storage Technology, Inc OLZ T CLZ ...

Page 14

... B IGURE ONTROLLED YTE ADDRESS A 18-0 CE# OE IGURE ESET OMMAND IMING © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 OEH T OES DATA VALID ROGRAM IMING IAGRAM FFH T DH ...

Page 15

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 ADDRESS A 18-0 CE# OE# WE 7-0 30H SETUP COMMAND IGURE HIP RASE IMING IAGRAM ADDRESS A 18 CE# OE# WE 7-0 20H SETUP COMMAND IGURE ECTOR RASE IMING IAGRAM © 1999 Silicon Storage Technology, Inc. ...

Page 16

... F 10 IGURE OFTWARE ATA ROTECT © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 T PCH 1820 1822 0418 041B T PAH 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. ...

Page 17

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 ADDRESS A 18-0 CE# OE# WE# DQ 7-0 NOTE: THIS TIME INTERVAL SIGNAL CAN DEPENDING UPON THE SELECTED OPERATION MODE IGURE ATA OLLING IMING ADDRESS A 18-0 CE# T OEH OE WE NOTE: THIS TIME INTERVAL SIGNAL CAN DEPENDING UPON THE SELECTED OPERATION MODE. ...

Page 18

... NPUT UTPUT EFERENCE TO DUT F 14 IGURE EST OAD XAMPLE © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 REFERENCE POINTS (0.4 V) for a logic “0”. ILT (2.0 V) and AVEFORM TEST LOAD EXAMPLE TO TESTER ...

Page 19

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 Next Address F 15 IGURE YTE ROGRAM LOWCHART © 1999 Silicon Storage Technology, Inc. Start Initialize Address Execute Byte Program Setup Command Load Address and Data & Start Programming Read End of Write Detection No Programming Completed? ...

Page 20

... Initiated Wait Program/Erase Completed F 16 IGURE RITE AIT PTIONS © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 Toggle Bit Program/Erase Initiated Read byte Read same byte No Does DQ 6 match? Yes Program/Erase Completed 20 Data# Polling ...

Page 21

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 Increment Byte Address Next Sector Address F 17 IGURE ECTOR RASE LOWCHART © 1999 Silicon Storage Technology, Inc. Start Initialize Sector Address Execute Two Step Sector Erase Command End of Write Detection Erase No completed? Yes Read FF from ...

Page 22

... F 18 IGURE OFTWARE RODUCT © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 Execute Read ID Command (90H) to Enter Read ID mode Read Address 0000H MFG's Code = SST (BF) Read Address 0001H Device Code = 28SF040 (04) Execute Reset Command (FFH) to Exit from Read ID mode 309 ILL F18 ...

Page 23

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 PRODUCT ORDERING INFORMATION Device Speed Suffix1 SST28XF040 - XXX - XX © 1999 Silicon Storage Technology, Inc. Suffix2 - XX 23 Package Modifier leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up Unencapsulated die Operating Temperature C = Commercial = 0° to 70° Industrial = -40° ...

Page 24

... SST28VF040-250-4I- NH Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 SST28SF040-150-4C 309-02 1/99 ...

Page 25

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 PACKAGING DIAGRAMS .065 .075 Base Plane Seating Plane .015 .050 .070 .080 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. ...

Page 26

... Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32 EAD HIN MALL UTLINE ACKAGE SST ACKAGE ODE © 1999 Silicon Storage Technology, Inc. 4 Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 18.50 18.30 20.20 19.80 (TSOP) 26 1.05 0.95 .50 BSC .270 8.10 .170 7.90 0.15 0.05 32.TSOP-EH-ILL.2 309-02 1/99 ...

Page 27

... Megabit SuperFlash EEPROM SST28SF040 / SST28LF040 / SST28VF040 © 1999 Silicon Storage Technology, Inc 309-02 1/99 ...

Page 28

... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 1999 Silicon Storage Technology, Inc. SST28SF040 / SST28LF040 / SST28VF040 International Sales Representatives & Distributors (408) 523-7754 ...

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