HM538253BJ-7 Elpida Memory, Inc., HM538253BJ-7 Datasheet
HM538253BJ-7
Available stocks
Related parts for HM538253BJ-7
HM538253BJ-7 Summary of contents
Page 1
... RAM: 605 mW/550 mW/495 mW SAM: 358 mW/330 mW/303 mW Standby 38.5 mW max Masked-write-transfer cycle capability Stopping column feature capability Persistent mask capability Elpida Memory, Inc joint venture DRAM company of NEC Corporation and Hitachi, Ltd. 8-bit) E0163H10 (Ver. 1.0) (Previous ADE-203-264A/265 (Z)) Jul. 6, 2001 (K) 8-bit dynamic ...
Page 2
... Split transfer cycle capability Block write mode capability Flash write mode capability 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh TTL compatible Ordering Information Type No. Access Time HM538253BJ HM538253BJ HM538253BJ-10 100 ns HM538254BJ HM538254BJ HM538254BJ-10 100 ns ...
Page 3
... Pin Arrangement HM538253BJ Series HM538254BJ Series SI/ SI/ SI/ SI/ DT RAS (Top view) Data Sheet E0163H10 HM538253B/HM538254B Series HM538253BTT Series ...
Page 4
HM538253B/HM538254B Series Pin Description Pin Name Function A0-A8 Address inputs I/O0-I/O7 RAM port data inputs/outputs SI/O0-SI/O7 SAM port data inputs/outputs RAS Row address strobe CAS Column address strobe WE Write enable DT/OE Data transfer/output enable SC Serial clock SE SAM ...
Page 5
Block Diagram A0 – A8 Column Address Buffer Input Data Control Input Buffer I/O0 – I/O7 Data Sheet E0163H10 HM538253B/HM538254B Series A0 – – A8 Row Address Refresh Buffer Counter Row Decoder 0 511 511 Memory Array 0 ...
Page 6
HM538253B/HM538254B Series Pin Functions RAS (input pin): RAS is a basic RAM signal active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of ...
Page 7
DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all operations of the HM538253B/HM538254B. QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched ...
Page 8
HM538253B/HM538254B Series Table 1 Operation Cycles of the HM538253B/HM538254B (cont) Register Mnemonic Write Pers Code Mask W.M. WM CBRS — — — CBRR — Reset Reset CBRN — — — MWT Yes No Load/use Yes Use MSWT Yes No Load/use ...
Page 9
RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write)(DT/OE high, CAS high and DSF1 are low at the falling edge of R AS, and DSF1 is low at the falling edge of CAS): Mnemonic Code Mask Write Cycle (WE ...
Page 10
HM538253B/HM538254B Series same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS. Mask Register ...
Page 11
Color Register Set Cycle RAS CAS Address Row WE DT/OE DSF1 Color Data I/O Set color register Note: 1. I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care Data Sheet ...
Page 12
HM538253B/HM538254B Series Color Register Set Cycle RAS CAS Row Address WE DT/OE DSF1 I/O Color Data *1 Mode WE Low New mask mode Persistent mask mode High No mask I/O Mask Data (In new mask mode) Low: Mask High: Non ...
Page 13
SAM start address must be determined by read transfer cycle or masked write transfer cycle (split transfer cycle isn’t available) before SAM access, after power on, and determined for each transfer cycle. Use the stopping columns (boundaries) in the serial ...
Page 14
HM538253B/HM538254B Series edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the persistent mode can be supported. The row address of data transferred into RAM is determined by the address ...
Page 15
DR2. If the next split read transfer isn’t executed while data is read from data register DR2, data read begins from SAM start address 0 of data register DR1 after data is read from data register DR2. ...
Page 16
HM538253B/HM538254B Series MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. In this cycle, the boundary split register operation using stopping columns is possible ...
Page 17
First a read data transfer cycle is executed, and SAM start addresses are set. The RAM data is transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After ...
Page 18
HM538253B/HM538254B Series SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE ...
Page 19
Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Recommended DC Operating Conditions ( +70°C) Parameter Symbol Supply ...
Page 20
HM538253B/HM538254B Series DC Characteristics ( +70°C, V HM538253B/HM538254B -7 Parameter Symbol Min Max Min Max Min Operating current I — CC1 I — CC7 Block write current I — CC1BW I — CC7BW Standby current I — ...
Page 21
DC Characteristics ( +70°C, V HM538253B/HM538254B -7 Parameter Symbol Min Max Min Max Min Hyper page mode I — CC4 current *3 (HM538254B) I — CC10 Hyper page mode I — CC4BW *3 block write current I ...
Page 22
HM538253B/HM538254B Series Capacitance (Ta = 25° Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (I/O, SI/O, QSF) Note: 1. This parameter is sampled and not 100% tested. AC Characteristics ( +70°C, ...
Page 23
Common Parameter Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS ...
Page 24
HM538253B/HM538254B Series Read Cycle (RAM), Page Mode Read Cycle Parameter Access time from RAS Access time from CAS Access time from OE Address access time Read command setup time Read command hold time Read command hold time referred to RAS ...
Page 25
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in ...
Page 26
HM538253B/HM538254B Series Read-Modify-Write Cycle Parameter Read-modify-write cycle time RAS pulse width (read-modify-write cycle) CAS to WE delay time Column address to WE delay time OE to data-in delay time Access time from RAS Access time from CAS Access time from ...
Page 27
Flash Write Cycle, Block Write Cycle, and Register Read Cycle Parameter CAS to data-in delay time OE to data-in delay time CBR Refresh with Register Reset Parameter Split transfer setup time Split transfer hold time referred to RAS t Hyper ...
Page 28
HM538253B/HM538254B Series Read Transfer Cycle Parameter DT hold time referred to RAS DT hold time referred to CAS DT hold time referred to DT precharge time DT to RAS delay time SC to RAS setup time 1st SC to RAS ...
Page 29
Masked Write Transfer Cycle Parameter SC setup time referred to RAS RAS to SC delay time Serial output buffer turn-off time referenced to RAS RAS to serial data-in delay time RAS to QSF delay time CAS to QSF delay time ...
Page 30
HM538253B/HM538254B Series Split Read Transfer Cycle, Masked Split Write Transfer Cycle Parameter Split transfer setup time Split transfer hold time referred to RAS t Split transfer hold time referred to CAS t Split transfer hold time referred to column address ...
Page 31
Serial Read Cycle, Serial Write Cycle (cont) Parameter Serial data-in hold time Serial write enable setup time Serial wrtie enable hold time Serial write disable setup time Serial write disable hold time Notes measurements assume t 2. When ...
Page 32
HM538253B/HM538254B Series 20. XXX (min) IH ///////: Invalid Dout *20 Timing Waveforms Read Cycle (HM538253B) RAS t CAS t RAD t t ASR RAH Address Row WE I/O (Output) I/O (Input DTS ...
Page 33
Fast Page Mode Read Cycle (HM538253B) RAS t CSH t RCD CAS t RAD t ASR t t ASC RAH Address Row Column t RCS WE I/O (Output) t DZC I/O (Input) t DZO t t DTH DTS DT/OE t ...
Page 34
HM538253B/HM538254B Series Write Cycle Table 3 below applies to early write, delayed write, page mode write, and read-modify write. Table 3 Write Cycle State Menu Cycle RWM Write mask (new/old) Write DQs to I/Os BWM Write mask (new/old) Block write ...
Page 35
Early Write Cycle RAS t RCD CAS t t ASR RAH Address Row I/O (Output I/O W4 (Input DTS DTH DT/ FSR RFH DSF1 W1 WI ...
Page 36
HM538253B/HM538254B Series Delayed Write Cycle RAS CAS t t ASR RAH Address Row I/O (Output I/O W4 (Input DTH DTS DT/ RFH FSR W1 DSF1 WI ...
Page 37
Fast/Hyper Page Mode Write Cycle (Delayed Write) RAS t CSH t RCD CAS ASR ASC RAH Address Column Row I/O (Output I/O W4 (Input) t ...
Page 38
HM538253B/HM538254B Series RAS-Only Refresh Cycle (HM538253B) RAS t CRP CAS t t ASR RAH Row Address t OFF1 I/O (Output) t CDD t I/O OFF2 (Input) t ODD t t DTS DTH DT/ FSR RFH DSF1 CAS-Before-RAS Refresh ...
Page 39
Hidden Refresh Cycle (HM538253B) RAS t RCD CAS t RAD t t ASR t RAH t Address Row WE I/O (Output) t DZC I/O (Input) t DZO t t DTS DTH DT/ RFH FSR t FSC DSF1 CAS-Before-RAS ...
Page 40
HM538253B/HM538254B Series CAS-Before-RAS Reset Cycle (CBRR RAS t t RPC CAS Address I/O (Output) I/O (Input) DT/OE t FSR DSF1 SC Bi*1 Notes: 1. Bi, Bj initiate the boundary addresses. When a CBRR is executed ...
Page 41
Flash Write Cycle (HM538253B) RAS t CRP CAS Address WE t CDD t OFF1 I/O (Output) t OFF2 t ODD I/O (Input) t DTS DT/OE DSF1 HM538253B/HM538254B Series RAS t RCD t t ASR RAH Row t ...
Page 42
HM538253B/HM538254B Series Register Read Cycle (Mask data, Color data) (HM538253B) RAS t CAS t t ASR RAH Address Row I/O (Output) I/O (Input) t DTS t DTH DT/ FSR RFH DSF1 Note: ...
Page 43
Read Transfer Cycle 1 RAS t RCD CAS t RAD t t ASR RAH Address Row I/O (Output) t DTS DT/ FSR RFH DSF1 t SCC SC t SCA t SOH Valid Sout ...
Page 44
HM538253B/HM538254B Series Read Transfer Cycle 2 RAS t RCD CAS t RAD t t ASR RAH Address Row I/O (Output DTS DTH DT/ RFH FSR DSF1 t SRS ...
Page 45
Masked Write Transfer Cycle RAS t RCD CAS t t ASR RAH Address Row I/O (Output DTS DTH DT/ FSR RFH DSF1 t SRS SRZ SCA ...
Page 46
HM538253B/HM538254B Series Split Read Transfer Cycle (HM538253B) RAS t CRP CAS t ASR Address Row OFF1 I/O (Output) t DTS DT/OE t FSR DSF1 t STS SCA t SOH SI/O ...
Page 47
Masked Split Write Transfer Cycle (HM538253B) RAS CAS t ASR Address OFF1 I/O (Output) t DTS DT/OE t FSR DSF1 t STS SC Bi*2 Ym*1 SI/O (Output SIH SIS SI/O Valid Valid Sin Sin ...
Page 48
HM538253B/HM538254B Series Serial Read Cycle SE t SCC SCP SC t SCA t SOH SI/O Valid Sout Valid Sout (Output) Serial Write Cycle t SWH SE t SCC SIS SIH SI/O ...
Page 49
Hyper Page Mode Read Cycle (HM538254B) RAS t CSH t RCD CAS t RAD t ASR t t ASC RAH Address Row Column t RCS WE I/O (Output) t DZC I/O (Input) t DZO t t DTH DTS DT/OE t ...
Page 50
HM538253B/HM538254B Series CAS-Before-RAS Refresh Cycle (CBRN) (HM538254B RAS t RPC t CP CAS Address WE t CHZ t RHZ I/O (Output) DT/OE DSF1 Hidden Refresh Cycle (HM538254B) RAS t RCD CAS t RAD t t ASR t RAH ...
Page 51
Flash Write Cycle (HM538254B) RAS t CRP CAS Address WE t CDD t CHZ I/O (Output) t OFF2 t ODD I/O (Input) t DTS DT/OE DSF1 Data Sheet E0163H10 HM538253B/HM538254B Series RAS t RCD t t ASR ...
Page 52
HM538253B/HM538254B Series Register Read Cycle (Mask data, Color data) (HM538254B) RAS t RCD CAS t t ASR RAH Row Address I/O (Output) I/O (Input) t DTS t DTH DT/ FSR RFH DSF1 ...
Page 53
Split Read Transfer Cycle (HM538254B) RAS t CRP CAS t ASR Address Row CHZ I/O (Output) t DTS DT/OE t FSR DSF1 t STS SCA t SOH SI/O (Output) Valid ...
Page 54
HM538253B/HM538254B Series Masked Split Write Transfer Cycle (HM538254B) RAS CAS t ASR Row Address CHZ I/O (Output) t DTS DT/OE t FSR DSF1 t STS SC Bi*2 Ym*1 SI/O (Output SIH SIS SI/O Valid ...
Page 55
... Package Dimensions HM538253BJ/HM538254BJ Series (CP-40D) 25.80 26.16 Max 40 1 0.74 1.30 Max 1.27 0.43 ± 0.10 0.10 HM538253BTT/HM538254BTT Series (TTP-44/40DA) 18.41 18.81 Max 0.80 0.30 ± 0.10 1.005 Max 0.10 Data Sheet E0163H10 HM538253B/HM538254B Series 0.21 M 11.76 ± 0.20 2.40 0.50 ± 0.10 Unit: mm 9.40 ± 0.25 Unit – 5° 0.80 55 ...
Page 56
... HM538253B/HM538254B Series Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...