FS9704B-PCE Fortune Semiconductor Corporation, FS9704B-PCE Datasheet
FS9704B-PCE
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FS9704B-PCE Summary of contents
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REV. 4.2 FS970X-DS-42_EN Datasheet FS970X 5,000/50,000 counts DMM analog front end. FEB 2007 ...
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... Fax：886-2-28094874 www.ic-fortune.com This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed by Fortune Semiconductor Corporation as a result of the use of this product. No rights under any patent accompany the sale of the product. ...
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Contents 1. GENERAL DESCRIPTION................................................................................................................... 5 2. FEATURES.......................................................................................................................................... 5 2.1 General Features (FS9701A example) ....................................................................... 5 2.2 Measurement Range (FS9701B as an example) ..................................................................... 6 3. ORDERING INFORMATION................................................................................................................. 6 4. ELECTRICAL CHARACTERISTICS..................................................................................................... 6 5. BLOCK-DIAGRAM .............................................................................................................................. 8 6. PACKAGING ...
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The Conversion of Digital Output & Equivalent Voltage........................................................31 11.7 The different output code of different models.......................................................................31 11.8 Other Control setting .............................................................................................................31 12. DIGITAL SIGNAL PROCESS ..............................................................................................................32 12.1 Frequency counter.................................................................................................................32 12.2 The reading process of frequency counter ...........................................................................32 12.3 Peak-hold ...
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... One of them can be connected to external resistor to build a x10 amplify circuit. The reading from the x10 signal into the ADC can still be of accuracy due to the excellent noise immunity of the amplifier. FS9701B 5000 / 5 FS9704B 80000 / 5 Chart 1. FS970X A/B series chips There are two different versions of FS970X with different specifications and functions. With the same micro processor FSµ ...
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... Hz, 500.0 Hz, 5.000 Khz, 50.00 Khz, 500.0 Khz, and 5.000 Mhz frequency. 9) Diode forward bias voltage test, with maximum forward voltage above peak hold detector 3. Ordering Information Product Number FS9701B FS9704B FS9701B-PCE FS9704B-PCE 4. Electrical Characteristics (VBAT = 9V, VSS = 0V, T =+25℃, unless otherwise indicated) A PARAMETER Zero Input Reading V ...
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PARAMETER VBAT Low Battery Detection Voltage VBAT Operating Current V =0, 500mV Scale IN R =1KΩ, 500Ω Scale IN Sleep Current ADC Current ACOP Current Comparator Current V =0. OSRC Source Capability ...
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Block-diagram AC-to-DC external network DMM Signal Input Conditioning Network Regulation network & precise zenner diode 9 V Battery 6. Packaging & Pins 6.1 LQFP 64 Pin Definition 17 FTC 18 TENM 19 ONEM 20 HUNK 21 TENK 22 ONEK ...
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Pin Description 64 PIN Pin Symbol LQFP Type pin 1 DPI VSSD 2-3 DIO XTALI,XTALO 4 DO BZR 5 DO IRQO 6-9 DIO AD<3:0> RD_ 11 DI WR_ 12 DI ALE 13 DI CS_ 14 DPI VCC ...
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Typical Application Circuit 1 D JmVP J3a TP6 TP5 mVP 9013 9013 D3 D6 4004 4004 COMMON 4004 4004 D7 4004 4004 1A/600V JmA1 mA F2 RA2 RA3 1 2 0.99,5W,10ppm 99,0.25W,10ppm 15A/600V ...
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Regulator VBAT S81250 IN OUT 9V Battery Graph 1. FS970X Regulator Block-diagram FS970X Regulator, as shown in Graph 1, needs to be connected with a S81250 low-cost regulator to convert the battery voltage above 6.8V to VDD voltage of ...
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Low Voltage Detector BATTER Y 9V Graph 2 Low Voltage Detector Low voltage detector is shown as Graph 2. After the voltage of VBAT is divided as LBS by resistor, it will flow into low voltage detector. The output ...
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AFT<6> AFT<4> ADG<7> SETADC<7:6> MISC1<4> MISC1<3> MISC2<1> Chart 2. Saving Mode Setup. 8.3 On/Off Power Output ENVDS/ ENVCS Graph 3 On/Off power output. VDDS and VCCS are the on/off power output of VDDP and VCC. The circuit is shown in ...
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Clock and Buzzer Generator 9.1 Clock Generator 4.0000 MHz Buzzer Graph 4 Clock Generator. Clock generator is shown in Graph 4. It can be connected to a 4.000 MHz crystal oscillator to produce 4.000 MHz clock frequency. It can ...
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Buzzer Generator FBP generator is controlled by ENBP. CNTBP and CMP1. The true value Chart is shown in Chart 4. Chart 4. FBP true value Chart The output of buzzer, BZR open drain output. It can be ...
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Function Network FUNCTION FUN1,2 FUN1 FUN2 MSB AFT<7:0> EXTD RCTEN ACDIV ACEN ENSCHMT CAPM SCP<7:0> SCMPH<3:0> SCMPL<1:0> SIN<7:0> BPFTR SINH<3:0> SRF<7:0> SRFH<1:0> SOSR<1:0> FTR RGD<7:0> RANGE<3:0> MODE<3:0> mA+uA mA 10A 99Ω 0.99Ω 0.01Ω ...
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Function Decoder Function decoder includes two set of input – MODE and RANGE. RANGE controls area network switch to determine measurement range, and MODE controls the function network signal to determine measurement mode. As shown in Chart 5, the ...
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Area Network Switch Combining area network switch to an external high-precision resistor becomes a measurement network. It transfers the signal of the sensor into suitable voltage range for ADC and measures the signal. The function decoder controls the measurement ...
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Power Supply Ω power supply flows directly into decay network, providing voltage as shown in Chart 8. Among them, cap is determined by function decoder. When cap=0, it’s not under capacity measuring mode. For DMM application, it represents ...
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Multiplexers and pre-filter Through multiplexers such as INHMUX, INLMUX, VRHMUX and VRLMUX, selectable ADC signals are FTIN, INL, VRH, and VRL. FTIN and INL first flow through a RC pre-filter, and then into full differential amplifier input INH and ...
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CPL is the negative input of CMP1, controlled by cap, cntd, SCMPL1:0, CAPM, and CAPTG. Details are shown in Chart 14. When cap=0 and cntd=0, the output of CPL is irrelevant to CAPM and CAPTG directly selected by ...
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Operation Amplifier and Comparator The block composed by operation amplifier and comparator include AC buffer block, full-wave rectifiers block, and comparator block. AGND CMPH Graph 6. AC buffer block. As shown in Graph 6, buffer block is controlled by ...
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As shown in Graph 7, the AC signal, inputting from RCTP and going through the rectifier, will obtain a full differential amplifier signal from ACHO and ACLO. It will then be connected to an external RC low-pass filter network to ...
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Analog to Digital Converter (ADC) 11.1 The operating theory of Σ-∆ ADC This high-resolution ADC adapts the modulation of delta and sigma. It samples the consecutive analog input signal by the sampling frequency of far higher frequency width input ...
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G v and represent respectively the gain and the offset voltage of ADC. They can both be affected during os manufacturing, and vary every single chip Under most of the applications of ADC, reference voltage is a fixed value ...
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With suitable gain option control, all kinds of measurement can be applied to the best dynamic range of ADC. Chart 15 shows the setup of three typical functions and ADG<5:0> in the application of DMM. ADG<5:0> Reference voltage gain（G Input ...
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There are two this kind of programmable digital filters in FS970X, namely, COMB1 and COMB2. Their output is SUM1 and SUM2 respectively. The number of COMB1is higher, often used to measure high resolution. And the number of COMB2 is lower; ...
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Reading and operation of ADC As described in 8.2, the circuitry of FS970X ADC might drift and causes an offset voltage because of manufacturing process. This might cause variance to the reading of ADC. To eliminate the offset variance, ...
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Low-resolution, high-speed output 11.5.2 When CYS<1:0>=00, the input of ADC becomes short; then, we can read the negative value of offset voltage of ADC from SUM2. It can be used When CYS<1:0>=11, the equivalent digit value of the voltage can ...
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Scale-type resistance measurement and Analog Bargraph 11.5.3 FS970X is equipped with fast ADC output SUM2. In the application of DMM, it can be used for Analog Bargraph display. However, as shown in Formula 6, when performing the scale-type resistor measurement, ...
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The Conversion of Digital Output & Equivalent Voltage Take the high resolution digital output of FS970X, the output, SUM1<23:0>, is the compensation value of 2/24bits. Whereas, SUM1<23> is the symbol bit – “0” = positive, and “1” = negative. ...
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Digital Signal Process Except digital filter, the digital signal process of FS970X includes frequency counter and peak-hold sampling process. 12.1 Frequency counter The frequency counter of FS970X is composed of time-based counter and signal counter. The physical value of ...
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Peak-hold sampling process As shown in the Chart 17, the reading of the output value of fast ADC meets the requirement of positive negative peak-hold of pulse bandwidth measuring in a matter of naro-second. The peak-hold sampling logic of ...
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Microprocessor interface 970x can directly connect to any microprocessor by CS_. WR_. RD_. ALE. AD3. AD2. AD1. AD0, and IRQO pins. It can also control read / write functions of registers, and handle interrupt. 13.1 Control register The control ...
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ADG<7:6> Performance setting of ADC SETADC<7:6> ENVDS & ENVCS, on/off power control setting SETADC<5:4> CYS<1:0> elimination mode setting of offset voltage of ADC SETADC<3:0> TPS1<1:0> and TPS2<1:0> the number of digital filter MISC1<7> CNTBP and CMP1of ENBP and MISC2<3> determine ...
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The interrupt process The measurements can be read by the microprocessor interface are high-resolution output of ADC, the low resolution output of ADC, positive-negative peak-hold value, the output of frequency counter…etc. In any of the registers, each new value ...
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Measurement Registers Address Register 0A KTB<23:0> 0B KSG<23:0> 0C POSPK<15:0> 0D NEGPK<15:0> 0E SUM2<15:0> 0F SUM1<23:0> Chart 21. all measurement value registers in the chip. All measurement registers and their corresponding address of FS970X are listed in Chart 21. ...
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Basic Measurement Application 14.1 DCmV 14.1.1 500 mV DCV DCmV 909KΩ Vx EXCEPT CAP 220pF 10K COMMON AGND Graph 17. Function network diagram of 500 mV. Address 00 01 Register RDG SIN Value 00h 00h Chart 22. 500 mV ...
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DC voltage DCV DCV R FUSE+PTC 1MΩ or 100KΩ or 10KΩ or 1KΩ Vx 10K COMMON AGND Graph 19. Function network diagram of DC voltage. Address 00 01 Register RDG SIN 0 5V~1000V x0h 10h Chart ...
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AC Voltage (ACV) C COMPENSATION DCV C DECOUPLE R FUSE+PTC 10MΩ Vx 1MΩ or 100KΩ or 10KΩ or 1KΩ 10K COMMON AGND Graph 20. Function network diagram of AC voltage. Address 00 01 Register RDG SIN 0.5V 10h 5Bh ...
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DC Current (DCA) mA+uA 10A 0.99Ω 0.01Ω COMMON 10K AGND Graph 21. Function network diagram of DC current. Address 00 Register RDG 5000uA, 500mA, 10A 00h 500uA, 5mA, 5A 00h Chart 27. DC current register setup. AS shown in ...
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AC Current (ACA) mA+uA 10A 0.99Ω 0.01Ω COMMON 10K AGND Graph 22. Function network diagram of AC current. Address 00 Register RDG 5000uA, 500mA, 10A 00h 500uA, 5mA, 5A 00h Chart 28. AC current register setup. As shown in ...
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Resistor (Ω) COMMON DCmV+OHM+CAP +DT+HFE+PKH 909KΩ EXCEPT CAP Rx 220pF AGND FUSE PTC DCV+OHM +CAP+HFE+PKH VOLT+OHM+ DT+CAP Graph 23. Function network diagram of resistor. Address 00 01 Register RDG SIN Value 89h 00h Chart 29. Resistor register setup. The ...
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... AFT<7:0> 07 MISC1<7:0> Chart 32. Capacitor range setup. Measuring capacitor value of FS9704B is to charge and discharge the resistor reference added by XOHM Pin to make an oscillation, and then calculate its oscillated cycle to get the capacitor value. VDD 3/4VDD 1/4VDD To calculate the cycle, we send the square wave that out from CAPTG to the frequency counter. When operating the frequency measurement, the necessary timer reference signal is FTB ...
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Diode Graph 25. Function network of diode measurement. Address 00 01 Register RDG SIN Setup value 01h 00h Chart 33. Diode register setup. Rev. 4.2 VB+ 1.5 kΩ OFF CHIP ON CHIP DT DCmV+OHM+CAP DT+HFE+PKH DT 909 kΩ 28 ...
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Package Outline LQFP64: plastic low profile quad flat package; 64 leads; body x1 pin 1 index DIMENSIONS (mm are the origlinal dimensions) A UNIT ...
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Attachment (1) OP-AMP Specifications (VDD = 6V, VSS = 0V, T =+25 , unless otherwise indicated) ℃ A Instrumentation Amplifier @ Gain = 30, Vref=0.5V, T PARAMETER Input Offset Voltage without AZ Rs<100 Input Offset Voltage with AZ Input ...