fs3861 Fortune Semiconductor Corporation, fs3861 Datasheet
fs3861
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fs3861 Summary of contents
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... Fortune Semiconductor Corp. Intelligent Charger Management Controller FS3861 Data Sheet Rev. 1.0 Dec. 2004 TD-0412012 CR-004 ...
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... Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed by Fortune Semiconductor Corporation as a result of the use of this product. No rights under any patent accompany the sale of the product. Fortune Semiconductor Corp. contains new product information. 2/34 FS3861 Fortune Rev. 1.0 ...
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... Charging Application Circuit........................................................................................... 12 10.1.3 Operation Flow Chart of Charging Application............................................................... 13 10.2 The Architecture of FS3861................................................................................................... 14 10.3 The organization of FS3861 MCU and its program & data memory space ..................... 14 10.3.1 Program Memory Organization ...................................................................................... 14 10.3.2 Data Memory Organization............................................................................................. 15 10.3.2.1 System Special Register ……………………………………..………………………… ...
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... The available 16-pin SSOP-16 package is offered for balanced area and cost effective requirements for size-sensitive applications. The FS3861 is suitable for the control of charge sequences of a variety of portable battery-powered applications, such as cellular phone’s travel and base charger devices, digital camcorder (DV), MP3 player ,etc ...
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... FS3861A-nnnV Customer’s compiled hex code can be programmed by FSC or customer itself into EPROM at factory before shipping. Note1: Code number (nnnV) is assigned for customer. Note2: Code number (nnn = 001~999); Version (V = A~Z). Fortune Semiconductor Corp. Package Type LQFP-64 SSOP-16 5/34 FS3861 Rev. 1.0 ...
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... Pin Configuration FS3861 SSOP16 Package FS3861 ICE LQFP64 Package Fortune Semiconductor Corp. 6/34 FS3861 Rev. 1.0 ...
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... Source or sink LED1 display 13 Battery temperature sensing input Battery ID-type selected by the voltage drop across the 14 series resistor. Battery ID is for identification of either thick, thin battery or other selected types 15 Battery input voltage 16 Charge control output to drive pass transistor 7/34 FS3861 Description SNS Rev. 1.0 ...
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... Voltage Reference 1.2V 1.4V 2.4V 2.8V 3.2V 3.4V 3.6V 4.0V 4.1V 4.2V 4.23V 4.25V 4.3V VPWM Embedded CMPNSEL[2:0] Microcontroller ENCVref MUX MUX Internal CMPPSEL[4:0] Oscillator GND OSC 8/34 FS3861 SNS ENCCref ENCC CURSEL[3: MUX VOLSEL[3:0] ENCV MUX TS VBATID VBAT SNS IC TEMP VPWM 1.2V 1.4V 1.5V 2.0V 2.4V 2.5V 2.6V 2.8V 3.0V 3.1V 3.2V 3.3V 3.4V 3.6V 3.9V 4.0V 4.1V 4.15V 4.2V 4.23V 4.25V 4.3V 25mA 50mA 75mA 100mA ...
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... I/O pins set as input mode The voltage select register VOSEL[3:0] = 4’b1100 (the register CVCTL at the data memory address=0BH), measured from voltage supply V region 4.35V to CC 5.50V T =0~60°C A External R=200kΩ 9/34 FS3861 Rating Unit °C °C °C/Sec Min. Typ. Max. Unit 4.35 5.0 5.5 ...
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... Typical Charging Scheme 10.1.1 Typical Charging Conditions and Phases The FS3861 uses flexible control schemes of charger’s current and voltage regulations in conjunction with the built-in 8-bit RISC-type MCU core running at typical 4 MHz for desired charge sequence controls during its operations embedded with the constant-current and constant-voltage regulations as well as the additional facilities of PWM voltages for user-defined intermediate voltage levels used for various applications ...
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... In brief summary, the typical Li+ battery charger’s procedures could be summarized in the following few steps: pre-charge conditioning, constant-current (C-C), constant voltage (C-V) stage, charge termination and monitor to re-charge, etc. There might have some individual charge’s current- or voltage-control schemes within the designated step to perform. Fortune Semiconductor Corp. 11/34 FS3861 Rev. 1.0 ...
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... Charging Application Circuit The Fig.2 shows the typical FS3861 application circuit used at base or travel charger devices of a variety of cellular phone and other portable devices. The above application circuitry shows the chip connected with an one-cell Li+ 4.2v battery, which features battery ID (at the VBATID input pin) and temperature sense output (at TS pin) for relevant controls ...
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... Operation Flow Chart of Charging Application Fig typical example of operation state diagram. Fortune Semiconductor Corp. Fig.10-3 Typical operation flow chart 13/34 FS3861 Rev. 1.0 ...
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... The Architecture of FS3861 The detailed architecture diagram of the FS3861 has already shown on Fig.7-1 for illustrations of its operations by the functional blocks, where the major facilities are constant-voltage (C-V) and constant-current (C-C) reference look-up table and regulation units as controlled by the MCU to realize the Li+ battery charge schemes. The FS3861 charger controller functions with illustrations of the current and voltage regulations, MCU, OTP ROM, and comparator implementing the linear-mode charge control ...
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... General data Memory (64 bytes SRAM) bit6 bit5 bit4 bit3 - - PD - 15/34 Reset State Bit2 Bit1 Bit0 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuu0uuuu uuuuuuuu uuu00000 VDDIF TMIF 0uu00000 VDDIE TMIE bit2 bit1 bit0 FS3861 WDT Reset State uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuu00000 0uu00000 Rev. 1.0 ...
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... VDDIF, VDDIE: VDD > VBAT Interrupt flag and enable. Used when there is only VBAT and VDD is off. VDDIF can wake up MCU if MCU is in sleep mode. bit0 TMIF, TMIE: 16-bit Timer Interrupt flag and enable. Fortune Semiconductor Corp. bit6 bit5 bit4 bit3 - - NORMIF OVLOIF UVLOIF VDDIF - - NORMIE OVLOIE UVLOIE VDDIE 16/34 FS3861 bit2 bit1 bit0 TMIF TMIE Rev. 1.0 ...
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... TMEN LED0EN LED0 - GPIO1 GPIO1PU SPWMO Unimplemented Unimplemented bit6 bit5 bit4 bit3 ENOVLO - - ENCMP < 5.5V. bit5 bit4 bit3 UVLO NORM CMPOUT 17/34 FS3861 Reset Bit2 Bit1 Bit0 - - - 00uu0uuu - - VDDIN uuuuuuuu 00000000 PWM [10] PWM [9] PWM [8] 00000000 PWM [2] PWM [1] PWM [0] 00000000 PWCS[2] PWCS[1] PWCS[0] uuu0u000 ...
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... CURSEL[1] CURSEL[0] 0100 0101 0110 145mA 170mA 265mA ±20mA ±20mA 1100 1101 1110 750mA 850mA 950mA bit2 bit1 VOLSEL[2] VOLSEL[1] VOLSEL[0] 0100 0101 0110 3.2V 3.4V 3.6V 1100 1101 1110 4.3V VPWM Reserved Reserved FS3861 , i.e. VDDIN is bit0 0111 360mA 1111 1050mA bit0 0111 4.0V 1111 Rev. 1.0 ...
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... CMPPSEL[1] 100 101 110 ICTEMP Reserved Reserved Reserved 00100 00101 00110 2.0V 2.4V 2.5V 01100 01101 01110 3.3V 3.4V 3.6V 10100 10101 10110 4.23V 4.25V 4.3V 11100 11101 11110 185mA 265mA 360mA ±20mA ±10% ±10% FS3861 bit0 CMPPSEL[0] 111 00111 2.6V 01111 3.9V 10111 60mA ±20mA 11111 410mA ±10% Rev. 1.0 ...
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... PWM[14 count (PDM[14 PWM[14]) as PWM[14] Fortune Semiconductor Corp. bit5 bit4 bit3 PWM [13] PWM [12] PWM [11] bit5 bit4 bit3 PWM [5] PWM [4] PWM [ The following figure shows the PDM definition 20/34 FS3861 bit2 bit1 bit0 PWM [10] PWM [9] PWM [8] bit2 bit1 bit0 PWM [2] PWM [1] PWM [0] Rev. 1.0 ...
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... PWCS[2:0] selects Pulse Density Modulation clock input source. Setting as below: PWCS [2:0] 000 Select - Fortune Semiconductor Corp. bit5 bit4 - PWEN 001 010 011 - - - 21/34 bit3 bit2 bit1 - PWCS[2] PWCS[1] PWCS[0] 100 101 110 4MHz/32 4MHz/64 4MHz/128 FS3861 bit0 111 4MHz/256 Rev. 1.0 ...
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... Source/2 Source/4 Source/8 bit5 bit4 bit3 LED0EN LED0 - 22/34 bit2 bit1 bit0 bit2 bit1 bit0 INS[2] INS[1] INS[0] 100 101 110 Timer Clock Timer Clock Timer Clock Source/16 Source/32 Source/64 bit2 bit1 bit0 GPIO2OEN GPIO2 GPIO2PU FS3861 111 Timer Clock Source/128 Rev. 1.0 ...
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... Enabled GPIO0 output 0 = Disable GPIO0 output bit1 GPIO0: GPIO0 output H/L bit0 GPIO0PU: Internal pull up 10kΩ. Not used : ADDRESS 14H Not used : ADDRESS 15H Fortune Semiconductor Corp. bit5 bit4 bit3 GPIO1 GPIO1PU SPWMO GPIO0OEN 23/34 FS3861 bit2 bit1 bit0 GPIO0 GPIO0PU Rev. 1.0 ...
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... Instruction Set The FS3861 instruction set consists of 37 instructions. Each instruction is a 16-bit word with an OPCODE and one or more operands. The detailed descriptions are shown as below. 11.1 Instruction Set Summary Instruction [W] ← [ ADDLW k [PC] ← [PC [W] ADDPCW [Destination] ← [f] + [W] ADDWF f, d [Destination] ← ...
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... Syntax Operation Flag Affected Description Cycle Example 1: ADDPCW Example 2: ADDPCW Example 3: ADDPCW 25/34 FS3861 Add ADDPCW [PC] ← [PC [W], [W] < 79h [PC] ← [PC ([W] – 100h), otherwise None The relative address are loaded into PC. 2 Before instruction 7Fh 0212h After instruction 0292h ...
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... Operation Flag Affected Description Cycle Example 1: ANDWF OPERAND,0 Example 2: ANDWF OPERAND,1 26/34 FS3861 Add W, f and Carry ADDWFC ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [ DC, Z Add the content of the W register, [f] and Carry bit the result is stored in the W register ...
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... Before instruction address (Node) : After instruction FLAG<2> address(OP1) If FLAG<2> address(OP2) Clear f CLRF f 0 ≤ f ≤ 255 [f] ← 0 None Reset the content of memory address f 1 Before instruction: WORK = 5Ah After instruction: WORK = 00h FS3861 Rev. 1.0 ...
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... If the result is 0, then the next fetched instruction is discarded and a NOP is executed instead of making it a two-cycle instruction Before instruction address (Node) : After instruction: : [FLAG] = [FLAG [FLAG address(OP1) If [FLAG] ≠ address(OP2) FS3861 Rev. 1.0 ...
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... IORWF ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [W] | [f] Z Inclusive OR the content of the W register and [f the result is stored in the W register the result is stored back in [f]. 1 Before instruction 88h, OPERAND = 23h After instruction 88h, OPERAND = ABh FS3861 Rev. 1.0 ...
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... MOVLW NOP f Syntax Operation Flag Affected Description Cycle RETLW Syntax Operation Flag Affected Description 30/34 FS3861 Move literal to W MOVLW k 0 ≤ k ≤ FFh [W] ← k None Move the eight-bit literal "k" to the content of the W register. 1 Before instruction: 23H W = 88h After instruction: ...
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... Operation Flag Affected Description Cycle Please make sure that all interrupt flags are cleared before running SLEEP; "NOP" command must follow HALT and SLEEP commands. 31/34 FS3861 Rotate left [f] through Carry RLF ≤ f ≤ FFh d ∈ [0,1] [Destination<n+1>] ← [f<n>] [Destination<0>] ← ← [f<7>] ...
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... Flag Affected Description Cycle Example 1: SUBWF OPERAND, 1 Example 2: SUBWF OPERAND, 1 Example 3: SUBWF OPERAND, 1 32/48 FS3861 Subtract W from f SUBWF ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [f] – [W] C, DC, Z Subtract the content of the W register from [f the result is stored in the W register ...
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... XORWF Syntax • Operation Flag Affected Description Cycle Example: XORWF k 33/34 FS3861 Exclusive OR W and f XORWF ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [W] XOR [f] Z Exclusive OR the content of the W register and [f the result is stored in the W register the result is stored back in [f] ...
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... BASIC 0.229 REF 0.20 0.33 0.008 0.20 0.008 0 ﾟ 8 ﾟ 0 ﾟ 0 ﾟ 8 ﾟ 0 ﾟ 5 ﾟ 10 ﾟ 15 ﾟ 5 ﾟ MO-137(AB) 34/34 FS3861 NOM MAX 0.064 0.069 0.006 0.010 0.059 0.012 0.010 0.025 BASIC 0.193 0.197 0.236 0.244 0.154 0.157 0.025 0.050 0.020 0.010 BASIC ...