fs3861 Fortune Semiconductor Corporation, fs3861 Datasheet - Page 14

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fs3861

Manufacturer Part Number
fs3861
Description
Intelligent Charger Management Controller
Manufacturer
Fortune Semiconductor Corporation
Datasheet
FS3861
10.2 The Architecture of FS3861
The detailed architecture diagram of the FS3861 has already shown on Fig.7-1 for illustrations of its operations by
the functional blocks, where the major facilities are constant-voltage (C-V) and constant-current (C-C) reference
look-up table and regulation units as controlled by the MCU to realize the Li+ battery charge schemes. The
FS3861 charger controller functions with illustrations of the current and voltage regulations, MCU, OTP ROM, and
comparator implementing the linear-mode charge control.
Note the built-in PWM (or called PDM, as named by the pulse density modulations) unit is complementary to the
fixed voltage reference for proper generation of reference voltage to use in the intermediate charge control. Their
VPWM levels subject to the PWM’s setting of the fraction’s bit and clock timing selects, as described in the later
section of data memory register definitions, so the PWM’s voltage level can then be used to perform specific
voltage regulation in constant-voltage charge control to activate the output pin CC (charge control).
10.3 The organization of FS3861 MCU and its program & data memory space
The FS3861 charger controller employs FSC’s proprietary RISC-architecture pipelined-mode high-performance
8-bit MCU core with built-in 1K Word program memory space and 64 Bytes of data memory space.
10.3.1 Program Memory Organization
CPU has a 10-bit program counter capable of address up to 1k x 16 program memory space. The reset vector is at
0000H and the interrupt vector is at 0004H.
Fortune Semiconductor Corp.
Rev. 1.0
14/34

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