CH7303A-TF Chrontel, CH7303A-TF Datasheet
CH7303A-TF
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CH7303A-TF Summary of contents
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... Chrontel CH7302/CH7303 HDTV / DVI Transmitter Features • Digital Visual Interface (DVI) Transmitter up to 165M pixels/second • DVI low jitter PLL with Emission Reduction • DVI hot plug detection • Analog YPrPb outputs for HDTV • HDTV support for 525p, 625p, 720p, 1080i and ...
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... CHRONTEL 1.0 Pin-Out .................................................................................................................................................................3 1.1 Package Diagram ..............................................................................................................................................3 1.2 Pin Description .................................................................................................................................................4 2.0 Functional Description..........................................................................................................................................6 2.1 TV Output Operation ........................................................................................................................................6 2.2 DVI Output .......................................................................................................................................................7 2.3 Input Interface...................................................................................................................................................8 3.0 Register Control..................................................................................................................................................13 3.1 Non-Macrovision Control Registers Index .....................................................................................................13 3.2 Control Registers Map ....................................................................................................................................15 3.3 Control Registers Description.........................................................................................................................16 4.0 Electrical Specifications .....................................................................................................................................25 4.1 Absolute Maximum Ratings ...........................................................................................................................25 4.2 Recommended Operating Conditions .............................................................................................................25 4.3 Electrical Characteristics ................................................................................................................................26 4.4 DC Specifications ...........................................................................................................................................26 4.5 AC Specifications ...........................................................................................................................................27 4 ...
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... VREF DGND 6 7 GPIO[1]/HPINT 8 GPIO[0] 9 HPDET DGND 12 DVDD 13 RESET* 14 SPD 15 SPC 16 NC Figure 2: 64-Pin LQFP Package – CH7302/CH7303 201-0000-051 Rev. 2.1, 5/21/2007 Chrontel CH7302/CH7303 CH7302/CH7303 48 HSYNC 47 VSYNC 46 D[12] 45 VDDV D[13] 42 D[14] 41 D[15] 40 DAC_GND 39 B/Pb 38 R/ ISET 34 DAC_GND ...
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... CHRONTEL 1.2 Pin Description Table 1: Pin Description Pin # Type Symbol VREF In/Out GPIO[1] / HPINT 8 In/Out GPIO[ HPDET RESET* 14 In/Out SPD 15 In SPC 19 In VSWING 22, 21 Out TLC, TLC* 25, 24 Out TDC0, TDC0* 28, 27 Out ...
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... CHRONTEL Table 1: Pin Description (contd.) Pin # Type Symbol 35 In ISET 37 Out Y/G (DAC1) 38 Out R/Pr (DAC2) 39 Out B/Pb (DAC0) 47 Out VSYNC 48 Out HSYNC 41 - 43, In/Out D[15] - D[0] Data[15] through Data[0] Inputs 46, 50 – 55, 58 –63 57 XCLK, XCLK* 1, 12, 49 Power DVDD 6, 11, 64 Power DGND 45 Power VDDV ...
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... CHRONTEL 2.0 Functional Description 2.1 TV Output Operation The CH7302/CH7303 can be selected to operate in one of several bypass modes for driving monitors requiring component video signals (HDTV, multi-sync monitors, etc.). All modes make use of the same set of DACs, and therefore cannot be used simultaneously. Table 2 describes the possible operating modes. A ‘p’ following a number in the Input Scan Type column indicates a progressive scan (non-interlaced) input where the number indicates the active number of lines per frame. An ‘ ...
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... CHRONTEL Table 4: EDTV Bypass Active Total Scan Type Resolution Resolution 720x480 858x525 Non-Interlaced 720x483 858x525 Non-Interlaced 720x480 856x525 Non-Interlaced 720x483 856x525 Non-Interlaced 720x576 864x625 Non-interlaced 2.1.2 RGB Bypass In RGB Bypass mode, data, sync and clock signals are input to the CH7302/CH7303 from a graphics device, and bypassed directly to the D/A converters to implement a second CRT DAC function ...
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... CHRONTEL 2.3 Input Interface 2.3.1 Overview Two distinct methods of transferring data to the CH7302/CH7303 are described. They are: • Multiplexed data, clock input at 1X the pixel rate • Multiplexed data, clock input at 2X the pixel rate For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7302/CH7303 is latched with both edges of the clock (also referred to as dual edge transfer mode or DDR) ...
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... CHRONTEL 2.3.5 Input Data Formats The CH7302/CH7303 supports 9 different data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge (rising or falling depending on the value of the MCP bit (Register 1Ch) – rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). The input data ...
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... CHRONTEL Table 6: Multiplexed Input Data Formats (IDF = 0, 1) IDF = Format = Pixel # Bus Data D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Table 7: Multiplexed Input Data Formats (IDF = 2, 3) IDF = Format = Pixel # P0a Bus Data D[11] G0[4] D[10] G0[3] D[9] G0[2] D[8] B0[7] D[7] B0[6] D[6] B0[5] D[5] B0[4] D[4] B0[3] Table 8: Multiplexed Input Data Formats (IDF = 4) IDF = Format = Pixel # P0a Bus Data D[7] Cb0[7] D[6] Cb0[6] D[5] Cb0[5] ...
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... CHRONTEL Table 9: Embedded Sync in Multiplexed Data Format (IDF=4) IDF = Format = Pixel # P0a Bus Data D[7] 1 D[6] 1 D[5] 1 D[4] 1 D[3] 1 D[2] 1 D[ this mode, the S[7:0] byte contains the following data: S[ during field 2, 0 during field 1 S[ during field (frame) blank, 0 elsewhere S[ during EAV (synchronization reference at the end of active video) ...
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... CHRONTEL Table 11: Non-multiplexed Input Data Formats (IDF = 10, 12) IDF = Format = Pixel # Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[ 16-bit RGB 16-bit YCrCb P0a P0b P0a P0b R[7] Not used Y[7] Not used R[6] Not used Y[6] Not used R[5] Not used Y[5] Not used R[4] Not used Y[4] Not used R[3] Not used Y[3] Not used ...
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... CHRONTEL 3.0 Register Control The CH7302/CH7303 is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device should retain all register values during power down modes. For details of CH7302/CH7303 registers read/write operation, please see AN-61 ...
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... CHRONTEL INPUT/OUTPUT CONTROLS DACBP DAC bypass DACG[1:0] DAC gain control DACT[2:0] DAC termination sense DES Decode embedded sync GOENB[1:0] Direction control for GPIO pins GPIOL[1:0] Read or Write Data for GPIO pins HSP H sync polarity control IDF[3:0] Input Data Format for D[15:0] MCP ...
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... CHRONTEL 3.2 Control Registers Map Table 13: Serial Port Register Map Register Bit 7 Bit 6 IR2 IR1 00h Reserved Reserved 03h HP7 HP6 05h VP7 VP6 06h BL7 BL6 07h Reserved Reserved 14h Reserved Reserved 1Ch Reserved Reserved 1Dh GOENB1 GOENB0 1Eh Reserved DES ...
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... CHRONTEL 3.3 Control Registers Description Display Mode Register 7 6 SYMBOL: IR2 IR1 TYPE: R/W R DEFAULT Register DM provides programmable control of the CH7302/CH7303 TV display modes, including input resolution (IR[2:0]), video output standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to Table 14 below when the HDTV bit (register 14h, bit 7) = ‘1’. These are the HDTV modes. ...
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... CHRONTEL Horizontal Position Register BIT SYMBOL: HP7 HP6 TYPE: R/W R/W DEFAULT 0 1 Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus HP[8] contained in the PO register (03h, bit 4). Increasing values move the displayed image position to the right, and decreasing values move the image position to the left ...
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... CHRONTEL HDTV Mode Register BIT SYMBOL: Reserved Reserved TYPE: R/W R/W DEFAULT HDTV (bit 0) enables the HDTV path. Clock Mode Register BIT SYMBOL: Reserved Reserved TYPE: R/W R/W DEFAULT XCM (bit 0) of register CM signifies the XCLK frequency for the data input. A value of ‘0’ is used when XCLK is at the pixel frequency (dual edge clocking mode) and a value of ‘ ...
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... CHRONTEL GPIO Control Register BIT SYMBOL: GOENB1 GOENB0 TYPE: R/W R/W DEFAULT HPIR (bit 3) of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7302/CH7303 to release the GPIO[1]/HPINT pin. When a hot plug interrupt is asserted by the CH7302/CH7303 (GPIO[1]/HPINT) the CH7302/CH7303 driver should read the DVIT bit in Register 20h to determine the state of the DVI termination ...
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... CHRONTEL Connection Detect Register BIT SYMBOL: HPIE Reserved TYPE: R/W R/W DEFAULT DACT[2:0] (bits 3-1) and SENSE (bit 0) of register CD provide a means to sense the connection the three DAC outputs. The status bits, DACT[2:0] correspond to the termination of the four DAC outputs. However, the values contained in these status bits ARE NOT VALID until a sensing procedure is performed ...
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... CHRONTEL Hot Plug Detect Register BIT SYMBOL: Reserved Reserved TYPE: R/W R/W DEFAULT HPDD (bit 2) of Register HPD disables the hardware hot plug detection function. This function (default on) tri-states the DVI outputs when the hot plug detect pin (HPDET) is pulled low in accordance with the DVI specification, revision 1 ...
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... CHRONTEL DVI PLL Divider Register BIT SYMBOL: Reserved Reserved TYPE: R/W R/W DEFAULT TPFBD[3:0] (bits 3-0) of register TPD control the DVI PLL feedback divider. The value should be set as shown in Table 16 depending on the input frequency range. TPFFD[1:0] (bits 5-4) of register TPD control the DVI PLL feed forward divider. The value should be set as shown in Table 16 depending on the input frequency range ...
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... CHRONTEL Table 17: Test Pattern Selection TSTP1 TSTP0 ResetDB (bit 3) of Register RES resets the datapath. When ResetDB is ‘0’ the datapath is reset. When ResetDB is ‘1’ the datapath is enabled. The datapath is also reset at power internally generated power-on-reset signal. ...
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... CHRONTEL Version ID Register BIT SYMBOL: VID7 VID6 TYPE DEFAULT: 0 Note For CH7302 this bit is 0, for CH7303 this bit is 1. Note: Register VID is a read only register containing the version ID number of the CH7302/CH7303 family. Product Number CH7302 CH7303 Device ID Register ...
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... CHRONTEL 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Symbol Description All power supplies relative to GND Input voltage of all digital pins T Analog output short circuit duration SC T Ambient operating temperature AMB T Storage temperature STOR T Junction temperature J T Vapor phase soldering (1 minute) VPS Note: 1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. ...
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... CHRONTEL 4.3 Electrical Characteristics = 0°C – 70°C, VDD =3.3V ± 5%) (Operating Conditions Symbol Description Video D/A Resolution Full scale output current Video level error I Total supply current VDD I VDDV (1.8V) current (15pF load) VDDV I Total Power Down Current PD 4.4 DC Specifications Symbol Description V SPD (serial port data) Output ...
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... CHRONTEL 4.5 AC Specifications Symbol Description f Input (XCLK) frequency XCLK t Pixel time period PIXEL DC Input (XCLK) Duty Cycle XCLK t XCLK clock jitter tolerance XJIT t DVI Output Rise Time DVIR (20% - 80%) t DVI Output Fall Time DVIF (20% - 80%) t DVI Output intra-pair skew SKDIFF t DVI Output inter-pair skew ...
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... CHRONTEL 4.6 Timing Information 4.6.1 Clock - Slave, Sync - Slave Mode XCLK XCLK D[11: Figure 5: Timing for Clock - Slave, Sync - Slave Mode Table 19: Timing for Clock - Slave, Sync - Slave Mode Symbol ...
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... CHRONTEL 5.0 Package Dimensions Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX 201-0000-051 Rev. 2.1, 5/21/2007 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 Figure 6: 64 Pin LQFP Package CH7302/CH7303 LEAD CO-PLANARITY E .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 29 ...
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... CHRONTEL 6.0 Revision History Revision # Date Section 1.0 3/11/2003 All 1.1 4/24/2003 Figure 2 Figure 1 General Description 6/23/03 1.11 7/10/03 Figure 1 Table 5 1.12 7/12/04 Register 1Eh 1.13 1/11/07 Register Ordering Information 2.0 1/17/07 All 2.1 5/21/07 3.0 30 Description First official release Changed pin out configurations. Added ‘AS’ to Figure 1 Revised description Table of Contents Added Added reset control block ...
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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part Number CH7302A-TF CH7302A-TF-TR CH7303A-TF CH7303A-TF-TR ©2007 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-051 Rev. 2.1, 5/21/2007 ...