NT5DS4M32EG-5 NanoAmp Solutions, Inc., NT5DS4M32EG-5 Datasheet
NT5DS4M32EG-5
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NT5DS4M32EG-5 Summary of contents
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... Differential clock input(CK & /CK) Ordering Information Part Number Package NT5DS4M32EG-5G 144-Balls NT5DS4M32EG-5 Green FBGA NT5DS4M32EG-6 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. • Data I/O transaction on both edges of Data strobe • ...
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... NanoAmp Solutions, Inc. Figure 1: PIN CONFIGURATION (Top View DQS0 DQS0 DM0 DM0 VSSQ VSSQ A A DQ4 DQ4 VDDQ VDDQ DQ6 DQ6 DQ5 DQ5 VSSQ VSSQ C C DQ7 DQ7 VDDQ VDDQ VDD VDD D D DQ17 DQ17 DQ16 ...
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... NanoAmp Solutions, Inc. Table 2: INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type # Input CK, /CK CKE Input /CS Input /RAS Input /CAS Input /WE Input DQS ~ DQS Input, Output Input Input, Output Input Input Power Supply DD SS ...
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... NanoAmp Solutions, Inc. Figure 2: FUNCTIONAL BLOCK DIAGRAM (1Mbit Bank) Bank Select CK,/CK ADDR LCKE LRAS LCBR LWE CK,/CK CKE /CS Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 32 Input Buffer ...
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... NanoAmp Solutions, Inc. Figure 3: SIMPLIFIED STATE DIAGRAM REGISTER WRITE WRITEA WRITE A POWER A PPLIED POWER Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. MRS MODE REFA IDLE SET A CT POWER ...
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... NanoAmp Solutions, Inc. FUNCTIONAL DESCRIPTION Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VREF & VTT 2. Start clock and maintain stable condition for minimum 200µ ...
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... NanoAmp Solutions, Inc. Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS latency, address mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... NanoAmp Solutions, Inc. Extended Mode Register Set (EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL ...
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... NanoAmp Solutions, Inc. Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory location (read cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst length are programmable and determined by address during the Mode Register Set command ...
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... NanoAmp Solutions, Inc. Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read command is issued by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock after tRCD from the bank activation. The address inputs (A0~A7) determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or interleave) and burst length(2,4,8, Full page) ...
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... NanoAmp Solutions, Inc. Burst Interruption Read Interrupted by Read Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied ...
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... NanoAmp Solutions, Inc. Read Interrupted by Precharge Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read precharge interval. Precharge command to output disable latency is equivalent to the /CAS latency. Figure 12: Burst Interrupted by Precharge (Burst Length = 8, /CAS Latency = 3) ...
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... NanoAmp Solutions, Inc. Write Interrupted by Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...
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... NanoAmp Solutions, Inc. Write Interrupted by Precharge & burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write recovery time (tWR) is required from the last data to precharge command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DM. ...
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... NanoAmp Solutions, Inc. BURST STOP COMMAND The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock only. The Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register ...
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... NanoAmp Solutions, Inc. AUTO-PRECHARGE OPERATION The Auto precharge command can be issued by having column address A8 High when a Read or a Write command is asserted into the DDR SDRAM low when Read or Write command is issued, normal Read or Write burst operation is asserted and the bank remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write cycle after tRAS (min) is satisfied ...
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... NanoAmp Solutions, Inc. Write with Auto Precharge high when Write command is issued, the write with Auto-Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR (min). ...
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... NanoAmp Solutions, Inc. PRECHARGE COMMAND The precharge command is issued when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock, CK. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR (min) ...
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... NanoAmp Solutions, Inc. SELF REFRESH A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption ...
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... NanoAmp Solutions, Inc. Table 5: Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage Temperature Power Dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. ...
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... NanoAmp Solutions, Inc. Table 7: DC Characteristic Recommended operating conditions (Voltage Reference to Vss=0V, VDD/VDDQ=2.5V±5%/2.5V±5%, TA 70C) Parameter Operating Current (One Bank Active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Cur- rent in Power Down ...
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... NanoAmp Solutions, Inc. Table 9: AC Operating Test Conditions (V = 2.5V±0.125V, TA=0 to 70C) DD Parameter Input Reference voltage for CK (for signal ended) CK and /CK signal maximum peak swing CK signal minimum slew rate Input levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition ...
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... NanoAmp Solutions, Inc. . Table 12: AC Characteristics Parameter CL=3 CK cycle time CL=2 CK high level width CK low level width DQS out access time from CK Output Access time from CK Data Strobe edge to Dout edge Read preamble Read postamble CK to Valid DQS-in DQS-in setup time DQS-in hold time ...
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... NanoAmp Solutions, Inc. Table 13: AC Characteristics (cont) Parameter Row cycle time Refresh cycle time Row active time /RAS to /CAS delay to read /RAS to /CAS delay to write Row precharge time Row active to Row active Last data in to Row Precharge Last data in to Row Precharge ...
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... NanoAmp Solutions, Inc. Table 14: Simplified Truth Table Command CKEn-1 Extended mode H register Register Mode Register H Set Auto Refresh H Entry Refresh Self Refresh Exit L Bank Active & Row Address H Auto Precharge Read & Disable Col H Auto Precharge Addr. Enable Auto Precharge Write & ...
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... NanoAmp Solutions, Inc. Table 15: Function Truth Table Current State /CS /RAS /CAS IDLE ROW ACTIVE READ ...
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... NanoAmp Solutions, Inc. Table 15: Function Truth Table Current State /CS /RAS /CAS READ with AUTO L L PRECHARGE WRITE with L H AUTO L L PRECHARGE PRE CHARGING ...
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... NanoAmp Solutions, Inc. Table 15: Function Truth Table Current State /CS /RAS /CAS REFRESHING ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don’t care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. ...
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... NanoAmp Solutions, Inc. Table 16: Function Truth Table for CKE Current State CKEn-1 CKEn SELF- L REFRESHING Both Bank Pre- charge L POWER DOWN ALL BANKS H IDLE Any State Other than listed above L L ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don’ ...
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... NanoAmp Solutions, Inc. Timing Figure 24: Basic Timing (Setup, Hold and Access Time @BL=2, CL=3) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 30 ...
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... NanoAmp Solutions, Inc. Figure 25: Multi Bank Interleaving READ (@BL=4, CL=3) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 31 ...
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... NanoAmp Solutions, Inc. Figure 26: Multi Bank Interleaving WRITE (@BL=4, CL=3) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 32 ...
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... NanoAmp Solutions, Inc. Figure 27: Auto Precharge after READ Burst (@BL=8) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 33 ...
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... NanoAmp Solutions, Inc. Figure 28: Auto Precharge after WRITE Burst (@BL=4) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 34 ...
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... NanoAmp Solutions, Inc. Figure 29: Normal WRITE Burst (@BL=4) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 35 ...
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... NanoAmp Solutions, Inc. Figure 30: Write Interrupted by Precharge & DM (@BL=8) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 36 ...
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... NanoAmp Solutions, Inc. Figure 31: Read Interrupted by Precharge (@BL=8) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 37 ...
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... NanoAmp Solutions, Inc. Figure 32: Read Interrupted by Burst stop & write (@BL=8, CL=3) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 38 ...
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... NanoAmp Solutions, Inc. Figure 33: Read Interrupted by Read (@BL=8, CL=3) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 39 ...
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... NanoAmp Solutions, Inc. Figure 34: DM Function (@BL=8) only for write /CK /CK / WRITE WRITE WRITE Command Command Command DQSS DQSS DQSS DQS DQS DQS WPRES WPRES WPRES DQ’s DQ’s DQ’ Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice ...
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... NanoAmp Solutions, Inc. Figure 35: Power Up Sequence & Auto Refresh (CBR) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 41 ...
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... NanoAmp Solutions, Inc. Figure 36: Mode Register Set Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Advance Information 42 ...
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... NanoAmp Solutions, Inc. IBIS : I/V CHARACTERISTICS FOR INPUT AND OUTPUT BUFFERS Reduced Output Driver Characteristics. 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of below figure 80 ...
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... NanoAmp Solutions, Inc. Table 17: Pulldown and Pullup IV Characteristics Pulldown Current(mA) Voltage Typical Typical (V) Low High 0.1 3.3 3.7 0.2 6.6 7.3 0.3 9.8 10.9 0.4 13.0 14.4 0.5 16.1 17.8 0.6 18.7 21.1 0.7 21.3 23.9 0.8 23.6 26.9 0.9 25.6 29.8 1.0 27.7 32.6 1.1 29.2 35.2 1.2 30.3 37.7 1.3 31.3 40.1 1.4 32.0 42.4 1.5 32.5 44.4 1.6 32.7 46.4 1.7 32.9 48.1 1.8 33.2 49.8 1.9 33.5 51.5 2.0 33.8 52.5 2.1 33.9 53.5 2.2 34.2 54.5 2.3 34.5 55.0 2.4 34.6 55.5 2.5 34.9 56.0 Temperature (Ambient) Typical 25° C Minimum70°C Maximum 0°C Vdd/Vddq Typical 2.50V / 2.50V Minimum 2.375V / 2.375V Maximum2.625V / 2.625V The above characteristics are specified under best, worst and normal process variation/conditions Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice ...
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... NanoAmp Solutions, Inc. Figure 37: Package Dimensions (144-Balls FBGA) 0.10 MAX 0.10 MAX 0.10 MAX 0.45 0.45 0.05 0.05 0.35 0.35 0.05 0.05 1.40 Max 1.40 Max Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. A1 INDEX MARK A1 INDEX MARK 12.0 12.0 12.0 12.0 <Top View> <Top View> ...
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... Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications ...