A1425A-PL84I Actel, A1425A-PL84I Datasheet

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... Energy Transfer) Threshold of 80 MeV-cm for All RT (RadTolerant) Devices • Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin Ceramic Quad Flat Pack • Offered as Class B and E-Flow (Actel Space Level Flow) • QML Certified Devices • 100% Military Temperature Tested (–55°C to +125° ...

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... A1425A A1460A A14100A = 20,000 Gates—ACT 3 Device Resources FPGA Device Type Logic Modules RT1020/A1020B 547 RT1280A/A1280A 1,232 RT1425A/A1425A 310 RT1460A/A1460A 848 RT14100A/A14100A 1,377 Note: Package Definition: CQFP = Ceramic Quad Flat Pack Contact your Actel sales representative for product availability 172 ...

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... A1280A Device (Prototyping Use) 172-Pin Ceramic Quad Flat Pack (CQFP) ACT 3 RT1425A Device 132-Pin Ceramic Quad Flat Pack (CQFP) A1425A Device (Prototyping Use) 132-Pin Ceramic Quad Flat Pack (CQFP) RT1460A Device 196-Pin Ceramic Quad Flat Pack (CQFP) A1460A Device (Prototyping Use) ...

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... Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 RT1020, A1020B Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 RT1280A, A1280A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 RT1425A, A1425A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 RT1460A, A1460A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 RT14100A, A14100A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Package Pin Assignments 84-Pin CQFP ...

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... RT1280A. These devices also have fully pin- and function- compatible commercially-equivalent devices for easy and inexpensive prototyping. The A1425A-CQ132C is used for the RT1425A, the A1460A-CQ196C is used for the RT1460A, and the A14100A-CQ256C is used for the RT14100A. ...

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... Development Tool Support The HiRel devices are fully supported by both the Actel Libero™ Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly ...

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The S-module, shown in Figure implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-type ...

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... The RadTolerant devices contain flexible I/O structures in that each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast setup time. In addition, the Actel Designer software tools can build a D-flip-flop, using a C-module, to register input and/or output signals The Actel Designer software development tools provide a design library of I/O macros ...

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... In accordance with applicable Actel device specification 1015, Condition D, 160 hours @ 125° hours @ 150°C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 2009 v3 ...

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... External Visual Notes: 1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B. Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The exceptions to Method 5004 are shown in notes 2 and 3 below. 2. Wafer lot acceptance is performed to Method 5007 ...

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... Supply Current CC( Dynamic V Supply Current CC(D) CC Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time min Not tested; for information only 0V MHz OUT Parameter ...

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... Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power + dissipation can be achieved. The power due to standby current is typically a small EQ 1-3 component of the overall power ...

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... Measurements are made over a range of frequencies at a fixed value of V capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown in RT1020, RT1280A, A1020B A1280A 3.7 5.8 22.1 12.9 32.1 23.8 ) 4.6 3.9 n/a n/a n/a n/a v3.1 RadTolerant FPGAs 1-4 active CC . Equivalent CC Table 1-7. RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A 6.7 7.2 10.4 1.6 0.7 0.9 1-9 ...

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... Table 1-8 • Fixed Capacitance Values for Actel FPGAs (pF) m Device Type n RT1020, A1020B p RT1280A, A1280A RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A Table 1-9 • Fixed Clock Loads (s1/s2 – ACT 3 Only) RT1020, A1020B, Device Type RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A v3 0 outputs 1 EQCR q1 ...

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... Average First Routed Array Clock Rate (f q1 Average Second Routed Array Clock Rate (f Average Dedicated Array Clock Rate ( Average Dedicated I/O Clock Rate ( RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Logic Modules (m) Input Switching (n) Outputs Switching (p) First Routed Array Clock Loads ( Second Routed Array Clock Loads (q ) ...

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RadTolerant FPGAs Input Delay I/O Module t INYL = 3.9 ns ARRAY CLOCK t CKH = 6 MAX = 55 MHz Figure 1-6 • RT1020, A1020B Timing Model Input Delays I/O Module t INYL = 3 ...

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... CLOCK t HCKH = 5 HMAX = 100 MHz t IOCKH = 3.5 ns I/O CLOCK (pad-to-pad) F IOMAX = 100 MHz Note: *Values shown for RT14100A –1 at worst-case military conditions. Figure 1-8 • RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Timing Model* Predicted Internal Delays Routing Delays Combinatorial Logic Module t RD1 = 1 RD4 = 2 ...

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RadTolerant FPGAs Parameter Measurement V CC GND In 50% 50 1.5V PAD 1. DLH t DHL Figure 1-9 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the Output under Test Figure ...

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... Figure 1-13 • Flip-Flops and Latches (RT1280A, A1280A SUD G, CLK E Q CLR D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-14 • Flip-Flops and Latches (RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A) D PRE Y E CLK CLR (Positive Edge Triggered ...

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RadTolerant FPGAs CLK PAD Figure 1-15 • Input Buffer Latches (R1280A, A1280A Figure 1-16 • Output Buffer Latches (RT1280A, A1280A PAD IBDL G CLKBUF PAD G t INSU t HEXT CLK t SUEXT D PAD ...

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RT1020, A1020B Timing Characteristics Table 1-10 • RT1020, A1020B Logic and Input Modules Worst-Case Military Conditions, V Parameter Logic Module Propagation Delays t Single Module PD1 t Dual Module Macros PD2 t Sequential Clock Latch G ...

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RadTolerant FPGAs Table 1-11 • RT1020, A1020B Output Module Worst-Case Military Conditions, V Parameter Global Clock Network t Input Low to High CKH t Input High to Low CKL t Minimum Pulse Width High PWH t Minimum Pulse Width Low ...

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RT1280A, A1280A Timing Characteristics Table 1-12 • RT1280A, A1280A Logic Module Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module ...

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RadTolerant FPGAs Table 1-13 • RT1280A, A1280A Input Module Worst-Case Military Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL t G-to-Y HIGH INGH t G-to-Y LOW INGL Input Module Predicted Routing Delays ...

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Table 1-14 • RT1280A, A1280A Output Module Worst-Case Military Conditions, V Parameter Description 1 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable-to-Pad Z to HIGH ENZH t Enable-to-Pad Z to LOW ENZL t Enable-to-Pad ...

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... RadTolerant FPGAs RT1425A, A1425A Timing Characteristics Table 1-15 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to Q CLR Logic Module Predicted Routing Delays t FO=1 Routing Delay ...

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... Table 1-16 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t Input Data Enable Hold (w.r.t. IOCLK Pad) IDEH t Input Data Enable Setup (w.r.t. IOCLK Pad) ...

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... RadTolerant FPGAs Table 1-17 • RT1425A, A1425A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High IOCKH (Pad to I/O Module Input) t Minimum Pulse Width High IOPWH t Minimum Pulse Width Low IOPWL t Minimum Asynchronous Pulse Width IOSAPW t Maximum Skew ...

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RT1460A, A1460A Timing Characteristics Table 1-18 • RT1460A, A1460A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to Q CLR ...

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RadTolerant FPGAs Table 1-19 • RT1460A, A1460A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t ...

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Table 1-20 • RT1460A, A1460A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High (Pad to I/O Module Input) IOCKH t Minimum Pulse Width High IOPWH t Minimum Pulse Width Low ...

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RadTolerant FPGAs RT14100A, A14100A Timing Characteristics Table 1-21 • RT14100A, A14100A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock-to Asynchronous Clear-to-Q CLR Logic Module ...

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Table 1-22 • RT14100A, A14100A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input Flip-Flop Data Hold INH t Input Flip-Flop Data Setup INSU t Input Data Enable Hold IDEH t Input Data ...

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RadTolerant FPGAs Table 1-23 • RT14100A, A14100A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input LOW to HIGH IOCKH (Pad to I/O Module Input) t Minimum Pulse Width HIGH IOPWH t Minimum Pulse ...

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... Input and compatible with standard TTL and CMOS specifications. In the RT1020, A1020B, RT1280, and A1280A devices, unused I/O pins are automatically driven LOW. In the RT1425, A1425A, RT1460, A1460A, A14100A devices, unused I/O pins are automatically tristated. IOCLK Dedicated (Hard-Wired) I/O Clock (Input) Not applicable for RT1020, A1020B, RT1280A and A1280A ...

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Package Pin Assignments 84-Pin CQFP Pin #1 Index Figure 2-1 • 84-Pin CQFP (Top View ...

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RadTolerant FPGAs 84-Pin CQFP Pin A1020B RT1020 Number Function Function I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 GND GND 9 I/O I/O 10 I/O I/O ...

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CQFP 132131130129128127126125124 Pin #1 Index Figure 2-2 • 132-Pin CQFP (Top View) 107106105104103 ...

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... I/O 53 I/O I/O 54 I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 GND GND I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 IOPCL, I/O IOPCL, I/O 65 GND GND I/O I/O 69 I/O I/O 70 I/O I/O v3.1 132-Pin CQFP Pin A1425A RT1425A Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 GND GND I/O I/O 77 I/O I I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O I/O 84 I/O I/O 85 I/O I/O 86 I/O I/O 87 I/O I/O 88 ...

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... CQFP Pin A1425A RT1425A Number Function Function 106 GND GND 107 108 I/O I/O 109 I/O I/O 110 I/O I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O 116 CLKA, I/O CLKA, I/O 117 CLKB, I/O CLKB, I/O 118 PRA, I/O PRA, I/O 119 I/O I/O 120 I/O I/O 121 I/O I/O 122 GND GND 123 124 ...

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RadTolerant FPGAs 172-Pin CQFP 172 171 170 169 168 167 166 165 164 Pin #1 Index ...

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CQFP Pin A1280A RT1280A Number Function Function 1 MODE MODE 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...

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RadTolerant FPGAs 172-Pin CQFP Pin A1280A RT1280A Number Function Function 106 GND GND 107 108 GND GND 109 110 111 I/O I/O 112 I/O I/O 113 V V ...

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CQFP 196 195 194 193 192 191 190 189 188 Pin #1 Index Figure 2-4 • 196-Pin CQFP (Top View) 155 154 ...

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RadTolerant FPGAs 196-Pin CQFP Pin A1460A RT1460A Number Function Function 1 GND GND 2 SDI, I/O SDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 ...

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CQFP Pin A1460A RT1460A Number Function Function 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 I/O I/O 110 111 112 GND GND 113 I/O I/O 114 I/O I/O 115 ...

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RadTolerant FPGAs 256-Pin CQFP 256 255 254 253 252 251 250 249 248 Pin #1 Index Figure 2-5 • 256-Pin CQFP (Top View) ...

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CQFP Pin A14100A RT14100A Number Function Function 1 GND GND 2 SDI, I/O SDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 I/O I/O ...

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RadTolerant FPGAs 256-Pin CQFP Pin A14100A RT14100A Number Function Function 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 I/O I/O 110 GND GND 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O ...

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CQFP Pin A14100A RT14100A Number Function Function 211 I/O I/O 212 I/O I/O 213 I/O I/O 214 I/O I/O 215 I/O I/O 216 I/O I/O 217 I/O I/O 218 I/O I/O 219 CLKA, I/O CLKA, I/O 220 CLKB, I/O ...

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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( The following pins changed in the v3.0 • Pin ...

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