BT261KPJ Brooktree, BT261KPJ Datasheet
BT261KPJ
Available stocks
Related parts for BT261KPJ
BT261KPJ Summary of contents
Page 1
... Noise Gate Detect Vertical SYNC Processor D0–D7 RD* WR* A0 Brooktree Division • Rockwell Semiconductor Systems, Inc. • 9868 Scranton Road • San Diego, CA 92121-3707 Brooktree ® 619-452-7580 • 1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: apps@brooktree.com • L261_H Phase PCOUT Comparator HSYNC CLOCK ...
Page 2
... Ordering Information Model Number Bt261KPJ Copyright © 1997 Brooktree Corporation. All rights reserved. Print date: September 1993 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use ...
Page 3
... VSYNC Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OSC Count Low and High Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 HSYNC Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CLAMP Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ZERO Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIELD Gate Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Noise Gate Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Brooktree ® L261_H iii ...
Page 4
... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller HCOUNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Application Information Phase Locking With the 74HC4046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interfacing to the Bt218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interfacing to the Bt254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Parametric Information DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Brooktree ® L261_H iv ...
Page 5
... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree ® L261_H v ...
Page 6
... Bt261 Pinout Diagram Figure 9. Bt261 Suggested Register Settings Figure 10. Operation of the Bt261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 11. Interfacing the Bt218 Figure 12. Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13. Interfacing to the Bt254 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 7
... Pin Descriptions Grouped By Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Bt261 Suggested Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4. Operation on the Bt261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6. Absolute Maximum Ratings Table 7. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. AC Characteristics Table 9. Bt261 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Brooktree ® L261_H L T IST OF ABLES vi ...
Page 8
... L T IST OF ABLES vii 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 9
... Brooktree ® C IRCUIT D ESCRIPTION MPU Interface As seen in the functional block diagram, the Bt261 supports an MPU interface via (D0–D7, RD*, WR*, and A0). MPU operations are asynchronous to the clocks. Refer to the Timing Waveforms section for further information used to select either the internal 5-bit address register (A0 = logical zero) or the control register specifi ...
Page 10
... HCOUNT low register $1D HCOUNT high register $1E reserved $1F reserved Command register_0 specifies the threshold above the sync tip to use for sync Typically, the VIDEO input will be connected to the TTL-compatible CSYNC* L261_H Bt261 Addressed by MPU Brooktree ® ...
Page 11
... CSYNC*. HSYNC may also be configured as an input, enabling external circuitry to generate HSYNC and drive the phase comparator. Brooktree ® Two 12-bit noise gate start and stop registers specify at what horizontal count The sync noise gating is provided to filter incorrect horizontal sync information The HSYNC output may be three-stated via the command register ...
Page 12
... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller For each scan line that the sample is a logical zero, the VSYNC* output is a log- The FIELD output is clocked by VSYNC*. Therefore, FIELD start and stop Figure 1 illustrates the operation of the FIELD gate and FIELD output. L261_H Bt261 Brooktree ® ...
Page 13
... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 1. Operation of FIELD and CAPTURE Outputs Brooktree ® L261_H C D IRCUIT ESCRIPTION FIELD Output 7 ...
Page 14
... VSYNC MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller To capture a single frame of video in an interlaced system, the MPU resets the In a non-interlaced system, the MPU resets the capture bit (CR5) low, then sets L261_H Bt261 Brooktree ® ...
Page 15
... HCOUNT val- ue, which should be set to the number of pixels per line, minus 1. Figure 2. External VCO Configuration. Brooktree ® An on-chip phase comparator is available to compare the phase of HSYNC and If the falling edge of the noise-gated CSYNC* occurs before the falling edge of The output of the phase comparator is PCOUT and TTL-compatible The " ...
Page 16
... HCOUNT and a stop value less than HCOUNT until lock is verified in the active field. The status registers can be mon- itored to verify lock MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 17
... SR00 would dictate restarting the acquisition sequence outlined above to maintain phase lock. Similarly, SR05 may be monitored to determine locking sta- tus. Brooktree ® A second analog noise gate is activated through the phase-limit feature. This Both forms of noise gate can be used together for maximum acquisition range ...
Page 18
... C D IRCUIT ESCRIPTION Two Forms of Noise Gating Available Figure 3. (a) Actual Gate-Level Implementation of Phase Limiting and Noise Gating (b,c, and d) Minimized Block Diagrams Corresponding to Waveforms in Figure MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 19
... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 4. Phase-Comparator State Diagram Brooktree ® Two Forms of Noise Gating Available L261_H C D IRCUIT ESCRIPTION 13 ...
Page 20
... C D IRCUIT ESCRIPTION Two Forms of Noise Gating Available Figure 5. Examples of Phase Comparator Operation With Different Types of Error and Different Implementations of Phase Limiting and Noise Gating 14 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 21
... Figure 6). Phase-limit enable must be deactivated during this evaluation (CR10 = 0); otherwise, phase limiting will affect the ability to monitor the loop-ac- quisition time. Brooktree ® The Status Registers SR00 and SR05 Used in Automatic Phase CR37–CR30 contains the phase-lock line count. This register determines the Bit 5 of the status register is used by the phase-limiting circuitry to determine if The active period compared with the value in CR27– ...
Page 22
... The selected OSC input is divided down to the desired pixel clock rate and duty The generated pixel clock is synchronized to the falling edge of the noise-gated There are three ways of controlling the horizontal counter, as determined by CR07 and CR06 are (0,1 falling edge of the noise-gated CSYNC* does L261_H Bt261 Brooktree ® ...
Page 23
... CR07 and CR06 are (1,0): Resets H counter at HCOUNT only. Figure 7. Pixel Clock Output Timing When Generated From Higher Speed Brooktree ® Asynchronous (Unlocked) Pixel Clock Generation If a falling edge of the noise-gated CSYNC* occurs before the number of pixel ...
Page 24
... FIELD for interlaced, or the falling edge of VSYNC* if non-interlaced. RD* Read control input (TTL compatible logical zero, data is output onto D0–D7. RD* and WR* should not be asserted simultaneously MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Description L261_H Bt261 Brooktree ® ...
Page 25
... If RD logical one, D0–D7 are three-stated. AO Address control inputs (TTL compatible). A0 specifies whether the MPU is accessing the address register ( the control register specified by the address register (A0 = 1). VCC Power. GND Ground. Figure 8. Bt261 Pinout Diagram Brooktree ® Description OSC1 27 17 ...
Page 26
... C D IRCUIT ESCRIPTION Pin Descriptions 20 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 27
... TTL compatible OSC2 (011) TTL compatible OSC2* (100) ECL compatible OSC1, OSC1* (101) ECL compatible OSC2, OSC2* (110) reserved (111) reserved Brooktree ® I NTERNAL R EGISTERS A value of (01) forces the horizontal counter to be reset to zero at the beginning of every noise-gated CSYNC*. These modes should be selected when using a high– ...
Page 28
... If this bit is a logical one, both horizontal sync signals (recov- ered and either internally or externally generated) must be present to adjust the VCO frequency. If one is missing, the VCO frequency is not adjusted. If this bit is a logical zero, a missing horizontal sync signal will adjust the VCO frequency. L261_H Bt261 Brooktree ® ...
Page 29
... OSC drives CLOCK direct (11) reserved Brooktree ® These bits specify the maximum number of pixel clock cycles between the falling edge of noise-gated CSYNC* and the HSYNC signal (either internally or externally generated considered locked. If the number of pixel clock cycles between the falling ...
Page 30
... If lock is not maintained for the specified number of scan lines, the phase limiter is dis- abled only if command bit CR22 is a logical one. SR05 is set to zero if lock is maintained for the specified number of scan lines. L261_H Bt261 Brooktree ® ...
Page 31
... Brooktree ® This bit reset if loss of lock is indicated. “Loss of lock” is defined as a greater phase error between noise-gated CSYNC* and generated HSYNC* than the phase-lock pixel count (CR27–CR24 reset by writing to com- mand bit CR12 ...
Page 32
... I R NTERNAL EGISTERS Status Register Figure 9. Bt261 Suggested Register Settings MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 33
... Gate) (HSYNC) Negative polarity, 4.7 s wide (CLAMP) One may CLAMP on burst back porch or sync tip (ZERO) (Field Gate) (VSYNC) This gives FIELD = 0, 1 for field one and two, respectively Brooktree ® NTSC(M) 12.2 MHz dec hex 63.556 s 779 30B Start Stop 61 ...
Page 34
... HSYNC Start/Stop High Data Bit Cascaded Value H11 H19 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller HSYNC Start/Stop Low L261_H Bt261 Brooktree ® ...
Page 35
... CSYNC* is recommended for the [start] value and a value corresponding to 2.5 s after the rising edge of CSYNC* is recommended for the [stop] value. For restoration of signals with subcarrier-encoded NTSC or PAL, the 7.8–9.4 s interval (12–15 percent of HCOUNT) following the color burst may be better for clamping a luminance signal with residual burst. Brooktree ® CLAMP Start/Stop Low D0 ...
Page 36
... CLAMP pulse to divert this energy. Both CLAMP and ZERO pins may be driven with the same timing MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller ZERO Start/Stop Low L261_H Bt261 Brooktree ® ...
Page 37
... Data Bit Cascaded Value H11 H19 H9 Values of one fourth HCOUNT and three fourths HCOUNT are recommended for start and stop values, resulting in an active high FIELD output (field one = 1, field two = 0). Brooktree ® FIELD Gate Start/Stop Low ...
Page 38
... RS343A 0,75 s Note: The Brooktree Applications Handbook and the RS343A and RS170A specifications contain minimum serration pulse widths. For wideband acquisition, the noise gate should be disabled by programming the start value greater and the stop value less than the number of pixels per line. ...
Page 39
... HCOUNT high register. Thus, the writing sequence should be [HCOUNT low] [HCOUNT high]. Values from $0000 (1) to $0FFF (4096) may be specified. This register should be written first during initialization to minimize indeterminate output activity. HCOUNT High Data Bit Cascaded Value H11 H19 H9 Brooktree ® HCOUNT Low ...
Page 40
... I R NTERNAL EGISTERS HCOUNT Register 34 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 41
... Brooktree ® A PPLICATION I NFORMATION Phase Locking With the 74HC4046 Applications that call for multiple resolutions with clock rates in the 9–18 MHz range may employ the circuit (Figure 10) shown with a 74HC4046 and a passive loop filter. Residual jitter can be less than 30 ns, which is subpixel but not as good as can be achieved with LC-tuned VCOs or VCXOs ...
Page 42
... Pixel Clock Monolithic CMOS HSYNC Line Lock Controller 470 86 500 k 100 pF 470 86 500 470 290 500 k MHz Reso- nant Crystal L261_H Damp ing ( 290 290 Hz 10 3.3 nF 300 pF 290 Hz Brooktree Bt261 0.74 0.74 0.74 ® ...
Page 43
... CLOCK. to the video timing controller and video DRAM controller. Figure 11. Interfacing the Bt218 Brooktree ® The Bt261 provides the ZERO and CLAMP signals required by the Bt218, in The HSYNC, VSYNC*, FIELD, and CAPTURE signals of the Bt261 interface L261_H ...
Page 44
... The Bt261 provides the ZERO and CLAMP signals required by the Bt252, in The HSYNC, VSYNC*, FIELD, and CAPTURE signals of the Bt261 interface Bt261 VIDEO ZERO CLAMP CLOCK CSYNC* ZERO CLAMP CLOCK Bt252 L261_H HSYNC VSYNC* FIELD To Video Timing CAPTURE Controller And DRAM Controller Brooktree Bt261 ® ...
Page 45
... VCC supply voltage is applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Brooktree ® The Bt261 provides the ZERO and CLAMP signals required by the Bt254, in ...
Page 46
... A I PPLICATION NFORMATION ESD and Latchup Considerations 40 30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 47
... This device employs high impedance CMOS devices on all signal pins. It should be handled as an ESD-sen- sitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can in- duce destructive latchup. Brooktree ® P ARAMETRIC ...
Page 48
... CIN 7 2.2 VIH GND–0.5 VIL IIH IIL CIN 7 VCC–1.0 VIH GND–0.5 VIL IIH IIL CIN 7 L261_H Bt261 Max Units VCC + 0.5 V VCC + 0.5 V 0 –1 A –1 VCC + 0 – VCC + 0.5 V VCC–1 – Brooktree ® ...
Page 49
... Notes: (1). VIH, VIL for RD*, HSYNC, and OSC inputs are tested at 3 and 0 V but guaranteed by characterization. 2. Test conditions (unless otherwise specified):"Recommended Operating Conditions." Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e Brooktree ® Symbol Min ...
Page 50
... Min Typ OSCmax 13.3 12.5 Fmax 33. 380 5 19 ICC 60 L261_H Bt261 Max Units 650 Brooktree ® ...
Page 51
... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Timing Waveforms Figure 13. MPU Read/Write Timing 1 Valid A0 RD*, WR* D0–D7 (Read) D0–D7 (Write) Brooktree ® Data Out (RD Data In (WR L261_H P I ARAMETRIC NFORMATION Timing Waveforms ...
Page 52
... P I ARAMETRIC NFORMATION Timing Waveforms Figure 14. Video/Output Timing Figure 15. Video Input/Output Timing HSYNC VIDEO (HSYNC) PCOUT 46 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller 19 18 Below Specified Threshold 3-State L261_H Bt261 19 Brooktree ® ...
Page 53
... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 16. Package Drawing—28–pin Plastic J-Lead (PLCC) Unless otherwise specified: Notes: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx 0.005 [0.127]. 3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers. Brooktree ® L261_H P I ARAMETRIC NFORMATION ...
Page 54
... Internal Register Section, HCOUNT register changed from 16-bit to 12-bit. The Application Information Section was revised; 0.1 F ceramic capacitor changed (this change applies to Figure 10 as well). Figures and 10 were revised MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
Page 55
... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree ® L261_H P I ARAMETRIC NFORMATION Revision History 49 ...
Page 56
... Brooktree ® Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707 (619) 452-7580 1(800) 2-BT-APPS FAX: (619) 452-1249 Internet: apps@brooktree.com L261_H printed on recycled paper ...