BT261 Brooktree, BT261 Datasheet
BT261
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BT261 Summary of contents
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller The Bt261 HSYNC Line Lock Controller is designed specifically for image cap- ture applications. Either composite video or TTL composite sync information is input via VIDEO. An internal sync separator separates horizontal and vertical sync infor- mation ...
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... Ordering Information Model Number Bt261KPJ Copyright © 1997 Brooktree Corporation. All rights reserved. Print date: September 1993 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller T C ABLE OF ONTENTS List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Circuit Description MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Video Input / Sync Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Horizontal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Horizontal Sync Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 HSYNC Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VSYNC* Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIELD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 CLAMP and ZERO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Capture Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External VCO Pixel Clock Generation ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller HCOUNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Application Information Phase Locking With the 74HC4046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interfacing to the Bt218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interfacing to the Bt254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Parametric Information DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision History ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree ® L261_H v ...
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... Pixel Clock Output Timing When Generated From Higher Speed Oscillator . . . . . . . . . . 17 Figure 8. Bt261 Pinout Diagram Figure 9. Bt261 Suggested Register Settings Figure 10. Operation of the Bt261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 11. Interfacing the Bt218 Figure 12. Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13. Interfacing to the Bt254 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller ...
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... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller List of Tables Table 1. Internal Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 2. Pin Descriptions Grouped By Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Bt261 Suggested Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4. Operation on the Bt261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6. Absolute Maximum Ratings Table 7. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. AC Characteristics Table 9 ...
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... L T IST OF ABLES vii 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... D ESCRIPTION MPU Interface As seen in the functional block diagram, the Bt261 supports an MPU interface via (D0–D7, RD*, WR*, and A0). MPU operations are asynchronous to the clocks. Refer to the Timing Waveforms section for further information used to select either the internal 5-bit address register (A0 = logical zero) or the control register specifi ...
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... HCOUNT low register $1D HCOUNT high register $1E reserved $1F reserved Command register_0 specifies the threshold above the sync tip to use for sync Typically, the VIDEO input will be connected to the TTL-compatible CSYNC* L261_H Bt261 Addressed by MPU Brooktree ® ...
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... VCO, there is a three-pixel-clock pipeline delay between CSYNC* and count zero. Horizontal Sync Separation The Bt261 separates horizontal sync information from CSYNC* by use of the hor- izontal noise gate register, which derives gated composite sync by removing equal- ization and serration pulses at half-line intervals. ...
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... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller For each scan line that the sample is a logical zero, the VSYNC* output is a log- The FIELD output is clocked by VSYNC*. Therefore, FIELD start and stop Figure 1 illustrates the operation of the FIELD gate and FIELD output. L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 1. Operation of FIELD and CAPTURE Outputs Brooktree ® L261_H C D IRCUIT ESCRIPTION FIELD Output 7 ...
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... Both CLAMP and ZERO may be programmed to be either active high or active low. Capture Output The Bt261 outputs a CAPTURE signal, which is a command register bit (CR05) synchronized to the vertical sync or FIELD signals. capture bit (CR5) low, then sets it high before the next rising edge of field. At the ...
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... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller External VCO Pixel Clock Generation An external VCO or pixel clock may be used to drive the Bt261, as shown in Figure 2. The pixel clock signal (from the VCO if one is used) is connected to any one of the OSC input pins (the one used must be selected by command bits CR00– ...
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... HSYNC pin. Two Forms of Noise Gating Available The Bt261 offers two forms of noise gating to remove half-line serration and equalization pulses during the vertical interval, which can cause loop disturbances and wavering at the beginning of the displayed field. The first is a digital noise gate that is programmed in pixel clock events following the falling edge of composite sync ...
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... This may not be ade- quate for some video signal sources, such as heterodyne VCRs (without time-base correction) or electronic still photography (e.g., floppy disk) cameras. If the Bt261 is programmed to permanently phase limit (CR22 set low), the phase-comparison duty is only ~0 ...
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... C D IRCUIT ESCRIPTION Two Forms of Noise Gating Available Figure 3. (a) Actual Gate-Level Implementation of Phase Limiting and Noise Gating (b,c, and d) Minimized Block Diagrams Corresponding to Waveforms in Figure MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 4. Phase-Comparator State Diagram Brooktree ® Two Forms of Noise Gating Available L261_H C D IRCUIT ESCRIPTION 13 ...
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... C D IRCUIT ESCRIPTION Two Forms of Noise Gating Available Figure 5. Examples of Phase Comparator Operation With Different Types of Error and Different Implementations of Phase Limiting and Noise Gating 14 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... RD* pin of the Bt261 is held low, then SR05 will indicate the lock status. This bit will set low when lock is held for the number of lines defined in the phase-lock line count. When this condition is observed while the phase-comparator output is viewed through two vertical intervals, the Bt261 response relative to the loop per- formance can be studied ...
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... The selected OSC input is divided down to the desired pixel clock rate and duty The generated pixel clock is synchronized to the falling edge of the noise-gated There are three ways of controlling the horizontal counter, as determined by CR07 and CR06 are (0,1 falling edge of the noise-gated CSYNC* does L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller clock cycles specified by HCOUNT, the horizontal counter is reset to zero by the falling edge of the noise-gated CSYNC*. CLOCK will be continuous and is re- synchronized to each falling edge of the noise-gated CSYNC*. This mode is used if the number of pixel clock cycles per scan line is known and is a fi ...
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... FIELD for interlaced, or the falling edge of VSYNC* if non-interlaced. RD* Read control input (TTL compatible logical zero, data is output onto D0–D7. RD* and WR* should not be asserted simultaneously MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Description L261_H Bt261 Brooktree ® ...
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... If RD logical one, D0–D7 are three-stated. AO Address control inputs (TTL compatible). A0 specifies whether the MPU is accessing the address register ( the control register specified by the address register (A0 = 1). VCC Power. GND Ground. Figure 8. Bt261 Pinout Diagram Brooktree ® Description OSC1 ...
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... C D IRCUIT ESCRIPTION Pin Descriptions 20 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... TTL compatible OSC2 (011) TTL compatible OSC2* (100) ECL compatible OSC1, OSC1* (101) ECL compatible OSC2, OSC2* (110) reserved (111) reserved Brooktree ® I NTERNAL R EGISTERS A value of (01) forces the horizontal counter to be reset to zero at the beginning of every noise-gated CSYNC*. These modes should be selected when using a high– ...
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... If this bit is a logical one, both horizontal sync signals (recov- ered and either internally or externally generated) must be present to adjust the VCO frequency. If one is missing, the VCO frequency is not adjusted. If this bit is a logical zero, a missing horizontal sync signal will adjust the VCO frequency. L261_H Bt261 Brooktree ® ...
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... CR16 is a logical zero). This bit is ignored if an external pixel clock is driving the CLOCK pin (command bit CR16 is a logical one). If the Bt261 goes out of lock, the phase limiter is auto- matically disabled until it is back in lock. If this bit is a logical zero, this function is overridden. ...
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... If lock is not maintained for the specified number of scan lines, the phase limiter is dis- abled only if command bit CR22 is a logical one. SR05 is set to zero if lock is maintained for the specified number of scan lines. L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Status Register This status register may be read by the MPU at any time and is not initialized. MPU write cycles to this register are ignored. SR00 corresponds to D0 and is the least significant bit. SR00 ...
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... I R NTERNAL EGISTERS Status Register Figure 9. Bt261 Suggested Register Settings MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Table 3. Bt261 Suggested Register Settings Pixel Clock Rate Line Rate (HCOUNT) Number of pixels minus 1 (Noise Gate) (HSYNC) Negative polarity, 4.7 s wide (CLAMP) One may CLAMP on burst back porch or sync tip (ZERO) (Field Gate) ...
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... HSYNC Start/Stop High Data Bit Cascaded Value H11 H19 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller HSYNC Start/Stop Low L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller CLAMP Start and Stop Registers These two 16-bit registers specify the horizontal count (in pixel clocks) at which to assert and negate the CLAMP out- put. The [start value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that CLAMP is set high. The [stop value] specifi ...
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... CLAMP pulse to divert this energy. Both CLAMP and ZERO pins may be driven with the same timing MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller ZERO Start/Stop Low L261_H Bt261 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller FIELD Gate Start and Stop Registers These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line ver- tical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between fi ...
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... MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller 261 Gate Minimum Stop Value Delay From End of Line 0,5 s 1.8 s 0,5 s 0,25 s Noise Gate Start/Stop Low L261_H Bt261 Minimum Noise-Gate Stop-Value Time 61,76 s 63. Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller HCOUNT Register This 12-bit register specifies the maximum number of pixel clocks to generate per horizontal line. In phase-locked applications, HCOUNT is the critical register that is resolution dependent. It should be programmed with the number of pixels per line required, minus 1. The other timing-dependent registers, including noise gate, ZERO, CLAMP, and HSYNC, will now all be programmed in terms of clock events, based upon the number of clocks per line defi ...
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... I R NTERNAL EGISTERS HCOUNT Register 34 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... LC-tuned VCOs or VCXOs. These have narrower tuning ranges. The loop parameters were obtained from a design program provided for the 74HC4046 with the Bt261’s phase comparator emulating the type 2 phase detector with 4 /VCC gain (Note 1). The type 1 second-order loop is designed for 10 dB ripple suppression in closed-loop response with a critically damped response and a tracking range of 4 percent, which is adequate for most stable sources (e ...
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... A I PPLICATION NFORMATION Phase Locking With the 74HC4046 Figure 10. Operation of the Bt261 with the 74HC4046A Table 4. Operation on the Bt261 with the 74HC4046A Tracking Oscilla Range tor Jitter 9–18 MHz < 17–26 MHz < 200 ppm < crystal ...
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... Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Interfacing to the Bt218 Figure 11 illustrates the interface of the Bt261 to the Bt218 Flash A/D Converter. The VIDEO input of the Bt261 connects to the VIN input of the Bt218 through ceramic capacitor. The sync slicing level of the Bt261 should be selected for optimum performance. ...
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... Interfacing to the Bt252 Interfacing to the Bt252 Figure 12 illustrates the interface of the Bt261 to the Bt252 Image Digitizer. The VIDEO input of the Bt261 connects directly to the CSYNC* output of the Bt252. As CSYNC TTL-compatible output, the highest sync slicing level should be selected on the Bt261. ...
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... Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Interfacing to the Bt254 Figure 13 illustrates the interface of the Bt261 to the Bt254 Image Digitizer. The VIDEO input of the Bt261 connects directly to the CSYNC* output of the Bt254. As CSYNC TTL-compatible output, the highest sync slicing level should be selected on the Bt261. ...
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... A I PPLICATION NFORMATION ESD and Latchup Considerations 40 30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller L261_H Bt261 Brooktree ® ...
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... This device employs high impedance CMOS devices on all signal pins. It should be handled as an ESD-sen- sitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can in- duce destructive latchup. Brooktree ® P ARAMETRIC ...
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... VIH 2.2 VIL GND–0.5 VIL IIH IIL IIL CIN 7 2.2 VIH GND–0.5 VIL IIH IIL CIN 7 VCC–1.0 VIH GND–0.5 VIL IIH IIL CIN 7 L261_H Bt261 Max Units VCC + 0.5 V VCC + 0.5 V 0 –1 A –1 VCC + 0 – VCC + 0 ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Table 7. DC Characteristics ( Parameter D0?–D7 Digital Outputs Output High Voltage (IOH = –400 A) Output Low Voltage (IOL = 6.4 mA) 3-state Current Output Capacitance PCOUT Output Output High Voltage (IOH = –400 A) Output Low Voltage (IOL = 3.2 mA) ...
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... Min Typ OSCmax 13.3 12.5 Fmax 33. 380 5 19 ICC 60 L261_H Bt261 Max Units 650 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Timing Waveforms Figure 13. MPU Read/Write Timing 1 Valid A0 RD*, WR* D0–D7 (Read) D0–D7 (Write) Brooktree ® Data Out (RD Data In (WR L261_H P I ARAMETRIC NFORMATION Timing Waveforms ...
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... P I ARAMETRIC NFORMATION Timing Waveforms Figure 14. Video/Output Timing Figure 15. Video Input/Output Timing HSYNC VIDEO (HSYNC) PCOUT 46 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller 19 18 Below Specified Threshold 3-State L261_H Bt261 19 Brooktree ® ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Figure 16. Package Drawing—28–pin Plastic J-Lead (PLCC) Unless otherwise specified: Notes: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx 0.005 [0.127]. 3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers. ...
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... P I ARAMETRIC NFORMATION Revision History Revision History Table 9. Bt261 Datasheet Revision History Revision Date Description G, H 09-16-93 In Table 1, HCOUNT start low/high register changed to HCOUNT low/high register. In the Internal Register Section, HCOUNT register changed from 16-bit to 12-bit. The Application Information Section was revised; 0.1 F ceramic capacitor changed (this change applies to Figure 10 as well) ...
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... Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree ® L261_H P I ARAMETRIC NFORMATION Revision History 49 ...
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... Brooktree ® Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707 (619) 452-7580 1(800) 2-BT-APPS FAX: (619) 452-1249 Internet: apps@brooktree.com L261_H printed on recycled paper ...