BT261 Brooktree, BT261 Datasheet - Page 37
BT261
Manufacturer Part Number
BT261
Description
30 Mhz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Manufacturer
Brooktree
Datasheet
1.BT261.pdf
(56 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
BT261KPJ
Manufacturer:
CONEXANT
Quantity:
8 831
Part Number:
BT261KPJ
Manufacturer:
BT
Quantity:
20 000
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
FIELD Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line ver-
tical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between fields
one and two (assuming a typical 2:1 interlaced video signal). By programming the FIELD start and stop values to
have an interval exceeding half a line (e.g. starting at 1/4 line time and stopping at 3/4 line time), the FIELD output
is low during field one if [start value] < [stop value] or high during field one if [start value] > [stop value], with tran-
sitions at every falling edge of VSYNC*. If [start value] = [stop value], FIELD will remain a constant logical one.
Values from $0000 (1) to $0FFF (4096) may be specified. Field edge coincides with VSYNC* falling edge.
cycles. The 16-bit FIELD gate start register is not updated until the write cycle to the FIELD gate start high register.
Thus, the writing sequence should be [field gate start low] [field gate start high].
cycles. The 16-bit FIELD gate stop register is not updated until the write cycle to the FIELD gate stop high register.
Thus, the writing sequence should be [field gate stop low] [field gate stop high].
in an active high FIELD output (field one = 1, field two = 0).
Brooktree
Data Bit
Cascaded Value
D4–D7 of FIELD gate start high are ignored during MPU write cycles and return a logical zero during MPU read
D4–D7 of FIELD gate stop high are ignored during MPU write cycles and return a logical zero during MPU read
Values of one fourth HCOUNT and three fourths HCOUNT are recommended for start and stop values, resulting
®
H11
D3
FIELD Gate Start/Stop
H19
D2
High
D1
H9
D0
H8
D7
H7
L261_H
D6
H6
D5
H5
FIELD Gate Start/Stop Low
D4
H4
FIELD Gate Start and Stop Registers
D3
H3
D2
H2
I
NTERNAL
D1
H1
R
EGISTERS
D0
H0
31