PCI9050-1 PLX Technology, Inc., PCI9050-1 Datasheet
PCI9050-1
Available stocks
Related parts for PCI9050-1
PCI9050-1 Summary of contents
Page 1
...
Page 2
...
Page 3
...
Page 4
...
Page 5
...
Page 6
...
Page 7
...
Page 8
...
Page 9
...
Page 10
...
Page 11
...
Page 12
...
Page 13
...
Page 14
...
Page 15
...
Page 16
...
Page 17
PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, ...
Page 18
... Notation added to timing diagrams and pin descriptions to indicate that in J mode, LAD[1:0] are valid address bits during the Address phase. Added pull-up resistor and EEPROM requirements to Section 8.1. xviii Byte Word Lword Comments © 2001 PLX Technology, Inc. All rights reserved. PCI 9050-1 Data Book, Version 2.0 ...
Page 19
... Sunnyvale, California, USA, with operations in the United Kingdom, Japan, and China. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 1.2 GENERAL DESCRIPTION The PCI 9050-1 provides a compact high performance PCI Bus Slave interface for adapter boards. The ...
Page 20
... PCI 9050-1 device by locking to the PCI 9050-1. PCI Bus Transfers up to 132 MB/s. Low-Power CMOS in 160-pin Plastic QFP Package (PQFP). PCI 9050-1 Major Features PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 21
... STOP# IDSEL DEVSEL# PERR# SERR# CLK RST# INTA# LOCK# EESK Serial EEDO EEDI EEPROM EECS PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. LAD[31:0] LA[27:2] LBE[3:0]# LINTi1 LINTi2 LCLK LHOLD LHOLDA LRESET# BCLKO CS[1:0]# USER0/WAITO# USER1/LLOCKo# USER2/CS2# USER3/CS3# ...
Page 22
...
Page 23
... The PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY# to insert PCI Bus wait state(s). PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 2.1.1.3 PCI Bus Little Endian Mode The PCI Bus is a Little Endian Bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane) ...
Page 24
... Configuration Registers Local Arbiter Feature Control Local Master Controller Local Control Address/Data Direct Slave FIFOs Data Figure 2-1. Local Bus Block Diagram © 2001 PLX Technology, Inc. All rights reserved. Local Bus when bursting to memory. The Local Bus is a 32-bit Local/Data Control ...
Page 25
... LAD Address, Data Bus • LBE# Local byte enables, indicating valid byte lanes PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 2.2.3 Local Bus Signals Signal usage varies upon application. There are four groups of Local Bus signals: • ...
Page 26
... LRDYi# is sampled by the PCI 9050-1. Data transfers are determined by an external device, which asserts LRDYi# to indicate a Data transfer is occurring. LRDYi# is not sampled until address-to-data or data-to-data wait states have expired. © 2001 PLX Technology, Inc. All rights reserved. Local Bus and ...
Page 27
... Non-Multiplexed 1 J 32-Bit Multiplexed PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 2.2.4.1 Local Bus Arbitration The PCI 9050-1 is the Local Bus Master. When the PCI Bus initiates a new transfer request, the PCI 9050-1 takes control of the Local Bus. Another device can gain control of the Local Bus by asserting LHOLD ...
Page 28
... Burst mode): • LAS0BRD[21:15, 12:6], • LAS1BRD1[21:15, 12:6], • LAS2BRD[21:15, 12:6], and/or • LAS3BRD[21:15, 12:6] PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Local Bus ...
Page 29
... LRDYi# Figure 2-4. PCI 9050-1 Single Cycle Read Note: NRDD is relevant only in a Burst cycle, where it determines the wait state between successive Data cycles. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns ADDR ADDR DATA Write Strobe Delay, Example=1 ...
Page 30
... If the Bterm mode bit is enabled and the BTERM# signal is asserted, the PCI 9050-1 asserts BLAST# only if its Read FIFO is full, its Write FIFO is empty transfer is complete. © 2001 PLX Technology, Inc. All rights reserved. Local Bus Burst-4 Lword Mode Burst ...
Page 31
... Generate internal wait states • Enable external wait control (LRDYi# input) • Enable type of Burst mode to perform PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 2.2.4.6 Local Bus Write Accesses For Local Bus writes, only bytes specified by a PCI Bus Master are written ...
Page 32
... Second Cycle 31 BYTE 0 15 Big Endian Figure 2-6. Big/Little Endian—16-Bit Local Bus © 2001 PLX Technology, Inc. All rights reserved. Local Bus Byte Lane Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [23:16] ...
Page 33
... Cycle 15 BYTE BYTE BYTE 0 Big Endian 7 0 Figure 2-7. Big/Little Endian—8-Bit Local Bus PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 0 BYTE 0 First Cycle 7 0 BYTE Section 2 Bus Operation 2-11 ...
Page 34
...
Page 35
... LRESET# is asserted when the PCI Bus RST# input is asserted ( delay) or the Software Reset bit is set (CNTRL[30]=1). PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 3.3 SERIAL EEPROM After reset, the PCI 9050-1 attempts to read the serial EEPROM to determine its presence ...
Page 36
... ST Microelectronics M93C46 or M93S46 or other compatible serial EEPROM. 1024 Empty 800 Load Data bits Figure 3-1. Serial EEPROM Memory Map PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Serial EEPROM 40h 32h words (16-bit data) ...
Page 37
... LOCAL 40h 0009 54h LOCAL 46h 0101 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Device ID. Vendor ID. Class Code. Class Code (revision is not loadable). Subsystem ID. Subsystem Vendor ID. (Maximum Latency and Minimum Grant are not loadable.) Interrupt Pin (Interrupt Line Routing is not loadable) ...
Page 38
... Configuration registers is fixed at 128 bytes. During initialization, the host writes FFFFFFFF to this register, then reads back FFFFFF81, determining a required 128 bytes of I/O space. The host then writes the base address to PCIBAR1[31:7]. © 2001 PLX Technology, Inc. All rights reserved. Internal Registers to the PCI 9050-1 ...
Page 39
... PCI Interrupt Pin. This register specifies the interrupt request pin (if any used. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Reset and Serial EEPROM Initialization 3.4.2 PCI Bus Access to Internal Registers ...
Page 40
...
Page 41
... Local Bus Lword or partial Lword. The PCI 9050-1 disconnects after one transfer for all Direct Slave I/O accesses. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. For higher data transfer rates, the PCI 9050-1 can be internal programmed to prefetch data during a PCI Burst Read ...
Page 42
... FIFO. For Read accesses mapped to PCI I/O space, the PCI 9050-1 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a single Address/Data cycle on the Local Bus. © 2001 PLX Technology, Inc. All rights reserved. Direct Data Transfer Mode PCI 9050-1 Local Bus ...
Page 43
... LA, ADS#, LW/R#, TRDY#, AD (data) Figure 4-4. Direct Slave Read Note: The figures represent a sequence of Bus cycles. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Clocks bits 4.2.1.5 Direct Slave PCI-to-Local Address Mapping Five Local Address spaces—Space 0, Space 1, Space 2, Space 3, and Expansion ROM— ...
Page 44
... Memory Local Base Address Figure 4-5. Local Bus Direct Slave Access Direct Data Transfer Mode Serial EEPROM 1 Initialize Local Configuration Registers Local Bus Hardware Characteristics 4 Local Bus Access Range PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 45
... LBE2# not used • LBE1# Address bit 1 (LA1) • LBE0# Byte Low Enable (BLE#)—LAD[7:0] PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Direct Slave Operation 8-Bit Bus—LBE[1:0]# are encoded to provide LA1 and LA0, respectively: • ...
Page 46
... Disconnect or Throttle TRDY# Empty Normal Full Normal Empty Disconnect or Throttle TRDY# © 2001 PLX Technology, Inc. All rights reserved. Response to FIFO Full or Empty Local Bus De-assert LHOLDA if Local Bus is busy 1 and wait for LHOLD to be de-asserted Normal, assert BLAST# Normal, assert BLAST# ...
Page 47
... EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 LAST WORD Timing Diagram 4-1. Initialization from Serial EEPROM PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 5us 10us 15us ...
Page 48
... Local Bus Master Drives the Bus 100ns 200ns RESPONSE ON THE PCI BUS LINTi1, LINTi2 ARE ACTIVE LOW LINTi1, LINTi2 ARE ACTIVE HIGH © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 500ns will not be reasserted until LHOLDA goes low 300ns 400ns ...
Page 49
... IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LA[27:2] LAD[31:0] LRDYi# USER[3:0] Timing Diagram 4-5. USER[3:0] as Inputs PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 100ns 500ns 750ns DATA D A BIT[2]=1 CMD BE BE Section 4 Direct Slave Operation 150ns ...
Page 50
... LRDYi# USER[3:0] 4-10 500ns USER0 SET AS OUTPUT CMD CMD BE Timing Diagram 4-6. USER[3:0] as Outputs Timing Diagrams 750ns 1000ns DATA DATA BIT[5]=0 A BIT[5]=1 CMD BE BE USER[3:0] PINS ARE OUTPUTS PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 1250ns ...
Page 51
... BLAST# LA[27:2] LAD[31:0] LRDYi# CS[3:0]# LBE[3:0]# WR# RD# LW/R# Note: CS[3:0]# Base Address is in the range of Spaces 3 through 0 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 100ns 200ns ADDR Timing Diagram 4-7. Chip Select [3:0]# Section 4 Direct Slave Operation 300ns 400ns ...
Page 52
... Read strobe delay = zero wait states Timing Diagram 4-8. C Mode, Direct Slave Single Write without Wait States (32-Bit Local Bus) 4-12 100ns ADDR DATA CMD BE Timing Diagrams 200ns 300ns ADDR A+4 DATA LBE PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 53
... Address-to-data = zero wait states Data-to-data = zero wait states Read strobe delay = zero wait states Timing Diagram 4-9. C Mode, Direct Slave Single Read without Wait States (32-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 100ns 200ns BE ADDR ...
Page 54
... Data-to-data = zero wait states (NRDD) Read strobe delay = zero wait states Timing Diagram 4-10. C Mode, Direct Slave Single Read with External (LRDYi#) Wait States (32-Bit Local Bus) 4-14 100ns 200ns BE © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 300ns 400ns D0 ADDR +4 ...
Page 55
... Write strobe delay = three wait states Write cycle hold = two wait states Timing Diagram 4-11. C Mode, Direct Slave Non-Burst Write with Wait States (32-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 500ns 750ns ADDR ...
Page 56
... Write strobe delay = two wait states, WR# not asserted because the delay is not ≤ NWAD Write hold cycle = one wait state Timing Diagram 4-12. C Mode, Direct Slave Non-Burst Write (8-Bit Local Bus) 4-16 250ns 500ns D4 ADDR © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 750ns 1000ns + PCI 9050-1 Data Book, Version 2.0 ...
Page 57
... Write strobe delay = zero wait states Write cycle hold = zero wait states Timing Diagram 4-13. C Mode, Direct Slave Non-Burst Read with BTERM# Enabled (32-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns D0 BE ...
Page 58
... Timing Diagram 4-14. C Mode, Direct Slave Non-Burst Read with Unaligned PCI Address (32-Bit Local Bus) 4-18 250ns C/BE[3:0]# ONLY ONE LWORD TRANSFERRED ADDR ADDRESS-TO-DATA WAIT STATES D0[15:0] D0[31:16] LBE LBE © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 500ns DATA A+4 LBE PCI 9050-1 Data Book, Version 2.0 ...
Page 59
... Address-to-data = one NRAD wait state Data-to-data = one NRDD wait state Read strobe delay = one wait state Timing Diagram 4-15. C Mode, Direct Slave Non-Burst Read with Prefetch (16-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns BE ADDR ...
Page 60
... Timing Diagram 4-16. C Mode, Direct Slave Non-Burst Read with Continuous Prefetch (8-Bit Local Bus) 4-20 500ns 1000ns Timing Diagrams 1500ns PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. F ...
Page 61
... BLAST# LA[27:2] LAD[31:0] LBE[3:0]# LRDYi# RD# WR# LW/R# Timing Diagram 4-17. C Mode, Direct Slave Burst Write with Delayed Local Bus (32-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns D3 D4 Section 4 Direct Slave Operation 500ns ADDR + ...
Page 62
... Write strobe delay = one wait state Write cycle hold = zero wait states Timing Diagram 4-18. C Mode, Direct Slave Burst Write with Wait States (16-Bit Local Bus) 4-22 250ns 500ns ADDR +4 D0[15:0] D0[31:16] D1[15:0] D1[31:16 © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 750ns 1000ns +8 +C D2[15:0] D2[31:16] D3[15:0] D3[31:16 ...
Page 63
... Burst enabled (Burst write of four Lwords) BTERM# disabled Data-to-address = two NXDA wait states Timing Diagram 4-19. C Mode, Direct Slave Burst Write with BTERM# Disabled PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns D10 D11 ...
Page 64
... Timing Diagram 4-20. C Mode, Direct Slave Burst Write with BTERM# Enabled (32-Bit Local Bus) 4-24 100ns 200ns Timing Diagrams 300ns 400ns ADDR + LBE PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. +10 D4 ...
Page 65
... BTERM# RD# WR# LW/R# Note: Burst enabled (Burst write of four Lwords) BTERM# enabled Timing Diagram 4-21. C Mode, Direct Slave Burst Write with BTERM# Enabled (8-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns ADDR A ...
Page 66
... Read strobe delays = zero wait states Timing Diagram 4-22. C Mode, Direct Slave Burst Read with Prefetch of Four Lwords (32-Bit Local Bus) 4-26 250ns BE ADDR + LBE PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 500ns ...
Page 67
... Data-to-data = zero wait states Read strobe delay = three wait states Timing Diagram 4-23. C Mode, Direct Slave Burst Read with Prefetch of Eight Lwords (16-Bit Local Bus) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns DP0 ...
Page 68
... Timing Diagram 4-24. C Mode, Direct Slave Burst Read with Prefetch of Four Lwords (8-Bit Local Bus) 4-28 500ns 750ns D0 BE ADDR A © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 1000ns 1250ns A+8 A PCI 9050-1 Data Book, Version 2.0 ...
Page 69
... Direct Slave read for Space 0 (same for Spaces 1, 2, and 3 and Expansion ROM) Prefetch eight Lwords, 32-bit Local Bus Timing Diagram 4-25. C Mode, Direct Slave Read with Read Ahead Mode Enabled (CNTRL[16]=1) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns D0 ...
Page 70
... PCI Write Release Bus Mode Enabled (CNTRL[18]=1) 4-30 500ns 750ns BE DISCONNECT + © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 1000ns 1250ns RELEASE BUS MODE 14 15 LBE PCI 9050-1 Data Book, Version 2.0 ...
Page 71
... Write Hold Bus Mode Enabled), PCI Read No Write Mode and PCI Read No Flush Mode (Read Ahead Mode) Enabled, PCI Read with Write Flush Mode Disabled, and PCI Delayed Read Mode Enabled (CNTRL[18:14]=01101) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 72
... LAD[31:0] LBE[3:0]# LRDYi# USER0/WAITO# RD# WR# LW/R# Timing Diagram 4-28. J Mode, Direct Slave Single Write, Local Bus Big Endian (32-Bit) 4-32 100ns ADDR 12345678 CMD BE © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 200ns 300ns 78563412 ADDR LBE PCI 9050-1 Data Book, Version 2.0 ...
Page 73
... Address-to-data = zero wait states Data-to-data = zero wait states Read strobe delay = zero wait states Timing Diagram 4-29. J Mode, Direct Slave Single Read, Local Bus Big Endian (32-Bit) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 100ns 200ns BE 78563412 ...
Page 74
... ADDR D0 D1 PCI Bus 12345678 AABBCCDD Local Bus 78563412 DDCCBBAA Timing Diagrams 300ns 400ns LBE 87654321 EEFFGGHH 12345678 21436587 HHGGFFEE 78563412 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 75
... Address-to-data = zero wait states Write strobe delay = zero wait states Write cycle hold = zero wait states Timing Diagram 4-31. J Mode, Direct Slave Burst Write, Local Bus Big Endian (16-Bit) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 200ns 300ns D0 D1 ...
Page 76
... Timing Diagram 4-32. J Mode, Direct Slave Burst Read, Local Bus Big Endian (32-Bit) 4-36 250ns BE ADDR LBE PCI Bus 12345678 AABBCCDD 87654321 Local Bus 78563412 DDCCBBAA 21436587 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Timing Diagrams 500ns EEFFGGHH HHGGFFEE ...
Page 77
... Address-to-data = one NRAD wait state Data-to-data = zero wait states Read strobe delay = three wait states Timing Diagram 4-33. J Mode, Direct Slave Burst Read, Local Bus Big Endian (16-Bit) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 250ns 500ns ADDR ADDR ...
Page 78
...
Page 79
... Local Address Space, and a chip select is not asserted. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Each 28-bit Chip Select Base Address register is programmed, as listed in the following table. Table 5-1. Chip Select Base Address Register ...
Page 80
... The following is a complete example of setting the Chip Select Base Address register with a range of 4000h, a base address of 24000h, and enabled: MSB=27 0000 0000 0010 0110 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. LSB=0 0000 0000 0001 ...
Page 81
... The PCI 9050-1 PCI Bus interrupt is a level output. Disabling an interrupt enable bit or clearing the cause(s) of the interrupt can clear an interrupt. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 6.2.2 Local Interrupt Input (LINTi[2:1]) The PCI 9050-1 provides two Local interrupts, LINTi[2:1] ...
Page 82
...
Page 83
... Subsystem ID 30h PCI Expansion ROM Base Address 34h 38h Maximum Latency 3Ch (Not Supported) (Not Supported) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. unused bits Vendor ID Command Class Code Revision ID PCI Bus ...
Page 84
... Register Address Mapping PCI EEPROM Writable PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Serial Writable ...
Page 85
... Value of 0 indicates fast back-to-back transfers can occur only to the same agent as the previous cycle. 15:10 Reserved. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Section 7 Registers Value after ...
Page 86
... Bit 7:0 Specific Register Level Programming Interface. None defined. 15:8 Subclass Encoding (80h). (Other Bridge Device). 23:16 Base Class Encoding. (Bridge Device). 7-4 Description Description Description © 2001 PLX Technology, Inc. All rights reserved. PCI Configuration Registers Value after Read Write Reset Yes No 0h Yes No ...
Page 87
... Note: Hardwired to 0. Memory Base Address. Memory base address for access to Local 31:7 configuration registers. Note: PCIBAR0 can be enabled or disabled by using CNTRL[13:12]. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Description Description Description Section 7 Registers ...
Page 88
... If I/O Space, bit 3 is included in the base address. 31:4 Base Address. Base address for access to the Local Address space. Note: PCIBAR2 can be enabled or disabled by setting or clearing LAS0BA[0]. 7-6 Description Description © 2001 PLX Technology, Inc. All rights reserved. PCI Configuration Registers Value after Read Write Reset Yes No ...
Page 89
... If I/O Space, bit 3 is included in base address. 31:4 Base Address. Base address for access to Local Address space. Note: PCIBAR4 can be enabled or disabled by setting or clearing LAS2BA[0]. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Section 7 Registers Value after ...
Page 90
... Subsystem Vendor ID. Unique Add-in Board Vendor ID. Register 7-18. (PCISID; 2Eh) PCI Subsystem ID Bit 15:0 Subsystem ID. Unique Add-in Board Device ID. 7-8 Description Description Description Description © 2001 PLX Technology, Inc. All rights reserved. PCI Configuration Registers Value after Read Write Reset Yes No 0 Mem: No I/O: Yes ...
Page 91
... Register 7-23. (PCIMLR; 3Fh) PCI Maximum Latency Bit Max_Lat. Specifies how often the device must gain access to the PCI Bus. 7:0 Value is a multiple of 1/4 µs increments. Not Supported. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Description Description Description ...
Page 92
... Note: Range (not Range register) must be power of 2. “Range register value” is two’s complement of range. 31:28 Reserved. (PCI address bits [31:28] are always included in decoding.) 7-10 Description Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset Yes ...
Page 93
... Note: Range (not Range register) must be power of 2. “Range register value” is two’s complement of range. 31:28 Reserved. (PCI address bits [31:28] are always included in decoding.) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Section 7 Registers ...
Page 94
... Yes Yes Yes Yes Yes Yes Yes Yes Yes No Value after Read Write Reset Yes Yes Yes Yes Yes Yes Yes Yes Yes No PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved ...
Page 95
... Note: Remap Address value must be a multiple of the Range (not the Range register). 31:28 Reserved. (Local address bits [31:28] do not exist in the PCI 9050-1.) PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Section 7 Registers Value after ...
Page 96
... This value must be ≤ NWAD for WR asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until the end of 31:30 the cycle (0-3). Used to extend data hold time. 7-14 Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset ...
Page 97
... This value must be ≤ NWAD for WR asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until the end of 31:30 the cycle (0-3). Used to extend data hold time. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Section 7 Registers Value after ...
Page 98
... This value must be ≤ NWAD for WR asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until the end of 31:30 the cycle (0-3). Used to extend data hold time. 7-16 Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset ...
Page 99
... Is asserted (0-3). This value must be ≤ NWAD for WR asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until the end of 31:30 the cycle (0-3). Used to extend data hold time. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Section 7 Registers Value after ...
Page 100
... This value must be ≤ NWAD for WR asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until the end of 31:30 the cycle (0-3). Used to extend data hold time. 7-18 Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset ...
Page 101
... The remaining most significant bits, excluding the first “1” found, define base address. 31:28 Reserved. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Description Description Description ...
Page 102
... Local Interrupt 2 Status. Value of 1 indicates interrupt active. Value indicates Interrupt not active. 6 PCI Interrupt Enable. Value of 1 enables PCI interrupt. 7 Software Interrupt. Value of 1 generates interrupt. 31:8 Reserved. 7-20 Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset Yes Yes 0 Yes Yes ...
Page 103
... PCI Read with Write Flush Mode. Value of 1 flushes a pending Read cycle if a Write cycle is detected. 15 Value of 0 does not effect pending reads when a Write cycle occurs (PCI r2.1-compatible). PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Description Section 7 Registers Value after Read ...
Page 104
... PCI 9050-1 remains in this reset condition until the PCI Host clears this bit. The contents of the PCI and Local Configuration registers are not reset. 31 Mask Revision. 7-22 Description © 2001 PLX Technology, Inc. All rights reserved. Local Configuration Registers Value after Read Write Reset ...
Page 105
... Internal pull-down Note: Internal resistor values are nominal and may vary widely from published values. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 8.2 PULL-UP/PULL-DOWN RESISTOR REQUIREMENTS Suggested values for external pull-up/pull-down resistors are from 1K to 10K Ohms. ...
Page 106
... EEPROM contents are loaded following PCI reset. If any of USER[3:0] multiplexed pins are configured as USER inputs (default functionality), they should be pulled to a known state. 8.2.4 NC Pins Do not connect No Connect pins. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. pull-up/pull-down ...
Page 107
... EEPROM Data Out Serial Data 1 EESK Clock 4 Total PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Pin Pin Type Number N/A 45, 67 Not Used. Test pin. Pull high for test or reduced power state. Tie low for normal operation. When TEST is pulled high, all outputs ...
Page 108
... TS 21 PCI O 1 STS 19 PCI © 2001 PLX Technology, Inc. All rights reserved. Pinout Function Multiplexed on the same PCI pins. A bus transaction consists of an Address phase, followed by one or more Data phases. The PCI 9050-1 supports both Read and Write bursts. Multiplexed on the same PCI pins. During the Address phase of a transaction, defines the bus command ...
Page 109
... Table 8-4. PCI System Bus Interface Pins (Continued) Signal Symbol Name RST# Reset SERR# System Error STOP# Stop TRDY# Target Ready Total PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Total Pin Pin Number Pins Type I 1 148 PU100K ...
Page 110
... PU100K I 138 8 mA © 2001 PLX Technology, Inc. All rights reserved. Pinout Function Provides a buffered version of the PCI clock for optional use by the Local Bus. Not in phase with the PCI clock. General purpose chip selects. The base and range of each may be programmed in the configuration registers. Local clock (required MHz ...
Page 111
... USER1/ User I LLOCKo# LLOCK Out User I USER2/CS2# Chip Select 2 Out User I USER3/CS3# Chip Select 3 Out Total PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Total Pin Pin Number Pins Type I 139 8 mA I/O ...
Page 112
... Pin Type Pin Number Pins I 1 129 PU100K © 2001 PLX Technology, Inc. All rights reserved. Pinout Function Indicates valid address and the start of a new Bus access. Asserted for the first clock of a Bus access. Asserted during the Address phase and de-asserted before the Data phase ...
Page 113
... Table 8-7. Mode-Dependent Local Bus Data Transfer Pins (Continued) Signal Symbol Name LA[27:2] Address Bus LAD[31:0] Data Bus LBE[3:0]# Byte Enables Total PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Total Pin Type Pin Number Pins O 122, 119-105 102-100, 98- I/O ...
Page 114
...
Page 115
... IH V Input Low Level IL Input Leakage I LI Current Three-State I Output Leakage OZ Current Power Supply Current PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. -65 to +150 °C -55 to +125 °C -0.5 to +7.0V V -0. +0. -0. +0.5V DD Supply Voltage ( ± ...
Page 116
... Figure 9-1. PCI 9050-1 Local Input Setup and Hold Waveform Table 9-5. AC Electrical Characteristics (Local Inputs) over Operating Range Frequency Min Local Clock Input 0 PCI Clock Input 0 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Local Inputs Max 40 MHz 33 MHz ...
Page 117
... LA[27:2] LAD[31:0] LBE[3:0]# LHOLDA LRESET# LW/R# RD# USER0/WAITO# USER1/LLOCKo# USER2/CS2# USER3/CS3# WR# Note: The values followed with an asterisk (*) are referenced from the PCI Bus. PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Valid T (Min) ns VALID 5% (Hold ...
Page 118
... Note: The ALE pulse width is independent of clock frequency. 9-4 Table 9-7. ALE Operation T (ns) from VALID Signal Local Clock Min/Max ALE LAD[31: PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. Local Outputs Pulse Width (ns) Min/Max N/A ...
Page 119
... PHYSICAL SPECIFICATIONS 10.1 MECHANICAL LAYOUT For 160-pin PQFP 120 121 160 Pin Max Figure 10-1. Mechanical Dimensions and Package Outline PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. 31.2 ±0.4 28 ±0.1 Index 0.65 0.3 ±0.1 0.8 ±0.2 Dimensions in millimeters 1 0– ...
Page 120
... LHOLD LHOLDA LRESET# BCLKO CS[1:0]# USER0/WAITO# USER1/LLOCKo# USER2/CS2# USER3/CS3# ADS# BLAST# LW/R# RD# WR# PCI LRDYi# 9050-1 BTERM# ALE MODE Figure 10-2. PCI 9050-1 Block Diagram © 2001 PLX Technology, Inc. All rights reserved. Typical Adapter Block Diagram I/O Controller Memory PCI 9050-1 Data Book, Version 2.0 ...
Page 121
... AD27 154 AD26 155 AD25 156 AD24 157 C/BE3# 158 IDSEL 159 V 160 SS PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. PCI 9050-1 Figure 10-3. Pin Assignments Section 10 Physical Specifications LAD10 78 LAD11 77 LAD12 76 LAD13 75 ...
Page 122
...
Page 123
... PLX offers to designers its PCI 9050-1 Bus Target Interface Chip for low cost adapters. Package Ordering Part Number 160-pin PQFP PCI 9050-1 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. low cost A.2 UNITED STATES AND INTERNATIONAL REPRESENTATIVES, AND DISTRIBUTORS A list of PLX Technology, Inc ...
Page 124
...
Page 125
... Direct Slave 4-4, 4-5 EROMBA 7-2, 7-13 invariance 2-1, 2-10 local bits 2-2 Local Bus initialization 4-3 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. local chip selects 5-1-5-2 local space registers 7-2, 7-10-7-17 local spaces 2-9 mapping 4-3 PCI base address registers 7-5-7-8 PCI system bus interface pins 8-4 ...
Page 126
... Delayed Read mode 1-2 Direct Slave 2-9, 4-2 descriptors, bus region 2-5, 4-3, 7-2, 7-6, 7-7, 7-8, 7-14-7-18, 8-8 device add-in board 7-8 bridge 7-4 chip select control provided 5-1 configuration header 3-4 ID 3-1, 3-3, 3-4, 7-1, 7-3 initialization select 8-4 Local Bus 2-2, 8-6 Master 2-4 non-PCI 2-2 other bridge 7-4 PCI 8-4 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 127
... Endian, Big 2-9-2-11 byte number and lane cross-reference 2-9 byte swapping 1-2, 7-14, 7-15, 7-16, 7-17, 7-18 control bits 2-9 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. conversion 4-3 Local Bus 2-9-2-11 on-the-fly conversion 4-3 timing diagrams 4-32-4-37 Endian, Little 2-9-2-11 byte number and lane cross-reference 2-9 ...
Page 128
... Big/Little Endian Mode 2-9-2-11 block diagram 2-2 Burst and Bterm modes 2-8 characteristics 4-3 control 4-3 cycles 2-5-2-9 data transfer pins 8-8-8-9 device 2-2 Direct Slave access 4-4 operation 4-1 interface 2-5-2-9 introduction 2-2-2-3 local signals 2-3 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 129
... PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. memory accesses 2-8, 3-4, 3-5, 7-5-7-8 address spaces 7-6-7-11 base address 7-5-7-8 BTERM# 2-8 commands aliased to basic 2-1 decode 7-10, 7-11 Direct Slave transfer 4-2 ...
Page 130
... Local Bus data transfer ADS# 2-3, 2-4, 2-8, 4-2, 8-8, 9-3 ALE 2-3, 2-4, 4-2, 8-8, 9-4 BLAST# 2-3, 2-8, 4-6, 8-8, 9-3 BTERM# 2-3, 2-6, 2-8, 4-17, 4-23, 4-24, 4-25, 7-14, 7-15, 7-16, 7-17, 7-18, 8-8 LA[27:2] 1-2, 2-2, 2-3, 8-9, 9-3 LAD[31:0] 1-2, 2-3, 2-9, 4-5, 8-9, 9-3, 9-4 LBE[3:0]# 1-2, 2-4, 4-5, 8-9, 9-3 LRDYi# 1-2, 2-3, 2-4, 2-5, 2-8, 2-9, 4-1, 8-8 LW/R# 2-4, 8-8 RD# 1-2, 2-5, 7-14, 7-15, 7-16, 7-17, 7-18, 8-3, 8-8, 9-3 WR# 1-2, 2-4, 7-14, 7-15, 7-16, 7-17, 7-18, 8-8, 9-3 pins, Local Bus support BCLKO 1-2, 8-6, 9-3, 10-3 CS[1:0]# 8-6, 9-3 CS2# 6-1, 7-21, 8-7, 9-3 CS3# 6-1, 7-21, 8-7, 9-3 LCLK 1-2, 2-3, 8-6, 9-1 LHOLD 2-5, 8-6 LHOLDA 2-5, 8-6, 9-3 LINTi1 4-8, 6-1, 8-6 LINTi2 6-1, 8-6 LLOCKo# 2-4, 6-1, 7-21, 8-7, 9-3 LRESET# 3-1, 4-9, 8-6, 9-3 MODE 2-5, 8-6 USER0 4-9, 4-10, 6-1, 7-21, 8-6, 9-3 USER1 6-1, 7-21, 8-7, 9-3 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 131
... Direct Slave access 4-1 Direct Slave example 4-2 Direct Slave Read Ahead mode 4-2 LAS0RR 7-10 LAS1RR 7-10 LAS2RR 7-11 LAS3RR 7-11 memory mapping 2-1-2-2 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. pins, PCI System Bus Interface PCIBAR0 7-5 PCIBAR2 7-6 PCIBAR3 7-7 PCIBAR4 7-7 PCIBAR5 7-8 timing diagrams 4-19, 4-20, 4-26-4-28 programmable ...
Page 132
... Single Cycle mode 2-8 single cycle read and write 2-7 software compatibility 7-1, 7-2 development 1-1 interrupts 7-20 PCI 4-4, 4-5 PLXMon 3-2 reset 3-1, 7-22 specifications See electrical specifications, physical specs or signal specs start bit 3-1, 3-2 states, four basic 2-3 STOP# 8-5, 10-3 PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved. ...
Page 133
... USER1 6-1, 7-21, 8-7, 9-3 USER2 6-1, 7-21, 8-7, 9-3 USER3 6-1, 7-21, 8-7, 9 8-3, 9-1, 10-3 DD vendor add-in board ID 7-8 ID 1-2, 3-3, 3-4, 7-1, 7-3 subsystem ID 3-3, 7-1 V 8-3, 10-3 SS PCI 9050-1 Data Book, Version 2.0 © 2001 PLX Technology, Inc. All rights reserved wait states control 2-5-2-6 counter configuration 2-5-2-6 generation 2-9, 4-1, 4-2, 8-8 generator 2-3, 8-6, 8-8 internal 8-8 internal programmable 2-6, 8-8 Local Bus 1-2, 2-6 NRAD 2-7, 7-14-7-18 NRDD 2-7, 7-14-7-18 NWAD 2-7, 7-14-7-18 NWDD 2-7, 7-14-7-18 NXDA 2-7, 7-14-7-18 ...
Page 134
...