AT32UC3A0512AU Atmel Corporation, AT32UC3A0512AU Datasheet - Page 238

• Manufacturer Part Number: AT32UC3A0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
24.13 Slave Mode
24.13.1
24.13.2
Figure 24-22. Slave Mode Typical Application Block Diagram
24.13.3
24.13.4
24.13.4.1
Definition
Application Block Diagram
Programming Slave Mode
Receiving Data
Read Sequence
Host with
Interface
Master
TWI
The Slave Mode is defined as a mode where the device receives the clock and the address from
another device called the master.
In this mode, the device never initiates and never completes the transmission (START,
REPEATED_START and STOP conditions are always provided by the master).
The following fields must be programmed before entering Slave mode:
1. SADR (SMR): The slave device address is used in order to be accessed by master
2. MSDIS (CR): Disable the master mode.
3. SVEN (CR): Enable the slave mode.
As the device receives the clock, values written in CWGR are not taken into account.
After a Start or Repeated Start condition is detected and if the address sent by the Master
matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave
ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a
condition is detected, EOSACC (End Of Slave ACCess) flag is set.
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the THR (TWI
Transmit Holding Register) until a STOP condition or a REPEATED_START + an address differ-
ent from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission
Complete) flag is set and SVACC reset.
TWD
TWCK
devices in read or write mode.
Host with TWI
Interface
Slave 1
Host with TWI
Interface
Slave 2
LCD Controller
Slave 3
R
R
AT32UC3A
VDD
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