AT32UC3A0512AU Atmel Corporation, AT32UC3A0512AU Datasheet - Page 425

• Manufacturer Part Number: AT32UC3A0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
28.8.1
Register Name:
Access Type:
Reset Value:
•
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
Table 28-9.
MODE: SDRAMC Command Mode
0
0
0
0
1
1
1
31
23
15
MODE
–
–
–
7
–
0
0
1
1
0
0
1
SDRAMC Mode Register
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The command will load the CAS latency from the Configuration Register and every other
value set to 0 into the Mode Register.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of
the cycle. Previously, an “All Banks Precharge” command must be issued.
The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed
regardless of the cycle. The command will load the PASR, DS and TCR from the Low Power Register and every
other value set to 0 into the Extended Mode Register.
Deep power-down mode. Enters deep power-down mode.
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
MR
Read/Write
0x00000000
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
AT32UC3A
24
16
–
–
8
–
0
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