AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 130
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AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 130 of 377
- Download datasheet (5Mb)
130
AVR32
ADDHH.W– Add Halfwords into Word
Architecture revision:
Architecture revision1 and higher.
Description
Adds the two halfword registers specified and stores the result in the destination word-register.
The halfword registers are selected as either the high or low part of the operand registers.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
31
15
0
1
If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
Rd ← operand1 + operand2;
addhh.wRd, Rx:<part>, Ry:<part>
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
OP1 = operand1, OP2 = operand2
Q:
V:
N:
Z:
C:
addhh.wR10, R2:t, R3:b
will perform R10 ← SE(R2[31:16]) + SE(R3[15:0])
0
1
29
0
1
Not affected
V ← (OP1[31] ∧ OP2[31] ∧ ¬RES[31]) ∨ (¬OP1[31] ∧ ¬OP2[31] ∧ RES[31])
N ← RES[31]
Z ← (RES[31:0] == 0)
C ← OP1[31] ∧ OP2[31] ∨ OP1[31] ∧ ¬RES[31] ∨ OP2[31] ∧ ¬RES[31]
12
28
0
11
1
Rx
1
1
25
8
0
24
0
7
0
0
6
0
0
X
5
0
4
Y
20
0
3
19
Rd
Ry
32000D–04/2011
0
16
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