AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 165
AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 165 of 377
- Download datasheet (5Mb)
32000D–04/2011
EOR – Logical Exclusive OR with optional logical shift
Architecture revision:
Architecture revision1 and higher.
Description
Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in
the destination register.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II, III.
Status Flags
Opcode:
15
31
0
1
15
0
Rd ← Rd ⊕ Rs;
Rd ← Rx ⊕ (Ry << sa5);
Rd ← Rx ⊕ (Ry >> sa5);
eor
eor
eor
{d, s} ∈ {0, 1, …, 15}
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Q:
V:
N:
Z:
C:
Format I:
Format II:
0
1
0
13
29
0
1
1
Rd, Rs
Rd, Rx, Ry << sa
Rd, Rx, Ry >> sa
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
Not affected
12
28
0
0
Rx
Rs
0
9
9
25
0
8
8
0
24
1
0
1
sa5
1
1
0
1
4
4
1
20
0
3
3
19
Ry
Rd
Rd
AVR32
0
0
16
165
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