AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 20
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AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
3. Pipeline
3.1
3.2
3.3
32002F–03/2010
Overview
Prefetch unit
Decode unit
AVR32UC is a pipelined processor with three pipeline stages: IF, ID and EX. All instructions are
issued and complete in order. Some instructions may require several iterations through the EX
stage in order to complete.
The following figure shows an overview of the AVR32UC pipeline stages.
Figure 3-1.
The follwing abbreviations are used in the figure:
The prefetch unit comprises the IF pipestage, and is responsible for feeding instructions to the
decode unit. The prefetch unit fetches 32 bits at a time from the instruction memory interface
and places them in a FIFO prefetch buffer. At the same time, one instruction, either RISC
extended or compact, is fed to the decode stage.
The decode unit generates the necessary signals in order for the instruction to execute correctly.
The ID stage accepts one instruction each clock cycle from the prefetch unit. This instruction is
then decoded, and control signals and register file addresses are generated. If the instruction
cannot be decoded, an illegal instruction or unimplemented instruction exception is issued. The
ID stage also contains a state machine required for controlling multicycle instructions.
The ID stage performs the remapping of register file addresses from logical to physical
addresses. This is used for remapping the stack pointer register into the SP_APP or SP_SYS
registers.
• IF - Instruction Fetch
• ID - Instruction Decode
• EX - Instruction Execute
• MUL - Multiplier
• ALU - Arithmetic-Logic Unit
• LS - Load/Store Unit
P re fe tc h u n it
IF
The AVR32UC pipeline stages.
D e c o d e u n it
ID
R e g file
R e a d
M U L
A L U
L S
R e g file
w rite
M u ltip ly u n it
L o a d -s to re
AVR32
A L U u n it
u n it
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