AT32UC3A4256S Atmel Corporation, AT32UC3A4256S Datasheet - Page 15
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AT32UC3A4256S
Manufacturer Part Number
AT32UC3A4256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256S
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
32002F–03/2010
ECR - Exception Cause Register
RSR_DBG - Return Status Register for Debug Mode
RAR_DBG - Return Address Register for Debug Mode
CONFIG0 / 1 - Configuration Register 0 / 1
COUNT - Cycle Counter Register
Table 2-3.
This register identifies the cause of the most recently executed exception. This information may
be used to handle exceptions more efficiently in certain operating systems. The register is
updated with a value equal to the EVBA offset of the exception, shifted 2 bit positions to the
right. Only the 9 lowest bits of the EVBA offset are considered. As an example, an ITLB miss
jumps to EVBA+0x50. The ECR will then be loaded with 0x50>>2 == 0x14. The ECR register is
not loaded when an scall, Breakpoint or OCD Stop CPU exception is taken. Note that for inter-
rupts, the offset is given by the autovector provided by the interrupt controller. The resulting ECR
value may therefore overlap with an ECR value used by a regular exception. This can be
avoided by choosing the autovector offsets so that no such overlaps occur.
When Debug mode is entered, the status register contents of the original mode is automatically
saved in this register. When the debug routine is finished, the retd instruction copies the con-
tents of RSR_DBG into SR.
When Debug mode is entered, the Program Counter contents of the original mode is automati-
cally saved in this register. When the debug routine is finished, the retd instruction copies the
contents of RAR_DBG into PC.
Used to describe the processor, its configuration and capabilities. The contents and functionality
of these registers is described in detail in
Can be used as a general counter to time for example execution time. Can also be used
together with COMPARE to implement a periodic interrupt for example for an OS timer. The con-
tents and functionality of this register is described in detail in
COUNT registers” on page
Name
SPL
CPL
COP
SIE
Bit
15:11
10:6
5:1
0
CPU control register
Reset
16
16
8
1
17.
Description
Slave Pending Limit. The maximum number of clock cycles the slave
interface can have a request pending due to the CPU owning the RAMs.
After this period, the CPU will lose arbitrartion for the RAM, and the
slave access can proceed.
CPU Pending Limit. The maximum number of clock cycles the CPU can
have a request pending due to the slave interface owning the RAMs.
After this period, the slave interface will lose arbitrartion for the RAM,
and the CPU access can proceed.
CPU Ownership Period. The number of cycles the CPU is guaranteed
to own the RAM after it has won the arbitration for the RAM. No
arbitration will be performed during this period.
Slave Interface Enable. If this bit is set, the slave interface is enabled.
Otherwise, the slave interface is disabled and any slave access will be
stalled.
Section 2.7 ”Configuration Registers” on page
Section 2.6 ”COMPARE and
AVR32
17.
15