AT32UC3A4256S Atmel Corporation, AT32UC3A4256S Datasheet - Page 62
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AT32UC3A4256S
Manufacturer Part Number
AT32UC3A4256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256S
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
6.2
6.3
6.4
6.4.1
6.4.2
32002F–03/2010
Memory interfaces
IF stage interface
EX stage interfaces
EX stage HSB master interface
EX stage HSB slave interface
The AVR32UC CPU has three memory interfaces:
The single master interface in the IF stage performs instruction fetches. All fetches are per-
formed with word alignment, except for the first fetch after a change-of-flow, which may use
halfword alignment. The IF stage can not perform writes, only reads are possible. Reads can be
perfomed from all addresses mapped on the HSB bus. Reads are performed as incrementing
bursts of unspecified length. The IF stage master interface will stall appropriately to support slow
slaves.
The EX stage separates between CPU accesses to the IRAM section, and accesses to
BOOT/HSB. Any access to the IRAM section are performed to dedicated, high-speed RAMs
implemented inside the memory controller. These fast RAMs are able to read or write within the
cycle they are initiated. This means that a load instruction in EX will have the read-data ready at
the end of the clock cycle for writing into the register file.
Any CPU access to the BOOT or HSB sections will use multiple clock cycles, as dictated by the
HSB semantics. Writes to the BOOT or HSB sections can be pipelined, and are performed as a
stream of nonsequential transfers, each taking one cycle unless stalled by the slave. If the slave
stalls the transfer, the CPU will stall until the slave releases the stall. CPU reads from the BOOT
or HSB sections are not pipelined, and transfer of a data therefore takes two clock cycles, one
cycle for the address phase, and one cycle for the data phase. The CPU will be stalled in the
data phase.
The AVR32UC CPU provides a slave interface into the high-speed RAMs that are implemented
inside the memory controller. This interface enables other parts of the system, like DMA control-
lers, to write or read data to or from the RAMs. The slave interface support bursts for both reads
and writes. If the high-speed RAMs for some reason cannot accept the transfer request, it will
reply by stalling the request until it can be serviced.
The arbitration priorities between the CPU and the slave interface for the RAMs can be con-
trolled by programming the CPU Control Register (CPUCR). The CPUCR is described in
2.5 on page
Assuming the memory interface is idle, and no memory transfers have been performed. Who-
ever requests access to the RAMs will win the arbitration and get access. If both the CPU and
the slave interface requests access, the CPU will win.
The source that won the arbitration can use the RAMs for as long as they require. If the other
source also has a pending request for use of the RAM, this source will have to wait maximum
the number of cycles specified by the SPL or CPL fields of CPUCR. The pending source will gain
• IF stage HSB master interface for instruction fetches
• EX stage HSB master interface for data accesses into BOOT or HSB sections
• EX stage HSB slave interface enabling other parts of the system to access addresses in the
IRAM section
11. Arbitration is performed according to the following rules:
AVR32
Section
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