AT32UC3B0512 Atmel Corporation, AT32UC3B0512 Datasheet - Page 313

• Manufacturer Part Number: AT32UC3B0512
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.6.4.9
21.6.4.10
Figure 21-22. Timeguard Operation
32059L–AVR32–01/2012
Baud Rate
TXEMPTY
TXRDY
Clock
Write
THR
TXD
Multidrop Mode
Transmitter Timeguard
Start
Bit
D0
D1
If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data
and address characters. Data has the parity bit zero and addresses have a one. By writing a one
to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be
transmitted as an address. Receiving a character with a one as parity bit will set CSR.PARE.
The timeguard feature enables the USART to interface slow devices by inserting an idle state on
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TG bit periods, in addition to the num-
ber of stop bits. As illustrated in
when TG has a non-zero value. If a pending character has been written to THR, the TXRDY bit
will not be set until this characters start bit has been sent. TXEMPTY will remain low until the
timeguard transmission has completed.
Table 21-8.
D2
D3
Baud Rate (bit/sec)
D4
D5
115200
14400
19200
28800
33400
56000
57600
1 200
9 600
D6
Maximum Baud Rate Dependent Timeguard Durations
D7
Parity
Bit
Stop
Bit
TG = 4
Figure
21-22, the behavior of TXRDY and TXEMPTY is modified
Start
Bit
Bit time (µs)
D0
69.4
52.1
34.7
29.9
17.9
17.4
D1
833
104
8.7
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Timeguard (ms)
Bit
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
TG = 4
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