AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 368

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.7.2
22.7.2.1
22.7.2.2
22.7.2.3
32059L–AVR32–01/2012
USB Device Operation
Introduction
USB reset
Power-On and reset
In device mode, the USBB supports full- and low-speed data transfers.
In addition to the default control endpoint, six endpoints are provided, which can be configured
with the types isochronous, bulk or interrupt, as described in
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
Figure 22-13 on page 368
Figure 22-13. Device Mode States
After a hardware reset, the USBB device mode is in the Reset state. In this state:
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
• All the endpoints are disabled, except the default control endpoint.
one).
describes the USBB device mode main states.
RESET
HW
| ID = 0
USBE = 0
“Device mode”
Reset
| ID = 0
& ID = 1
USBE = 0
state>
other
<any
USBE = 1
for further details.
Idle
Table 22-1 on page
352.
368