AT32UC3B1512 Atmel Corporation, AT32UC3B1512 Datasheet - Page 337
AT32UC3B1512
Manufacturer Part Number
AT32UC3B1512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1512
Flash (kbytes)
512 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1512-Z1UT
Manufacturer:
ROHM
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 337 of 684
- Download datasheet (11Mb)
• RIIC: Ring Indicator Input Change Flag
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
32059L–AVR32–01/2012
0: No change has been detected on the RI pin since the last CSR read.
1: At least one change has been detected on the RI pin since the last CSR read.
0: No Non Acknowledge has been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
This bit is cleared by writing a one to CR.RSTNACK.
0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive.
1: The Buffer Full signal from the Peripheral DMA Controller channel is active.
If USART does not operate in SPI Slave Mode:
ITER=0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER=1: Maximum number of repetitions has been reached since the last RSTSTA.
If USART operates in SPI Slave Mode:
UNRE=0: No SPI underrun error has occurred since the last RSTSTA.
UNRE=1: At least one SPI underrun error has occurred since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
0: The transmitter is either disabled or there are characters in THR, or in the transmit shift register.
1: There are no characters in neither THR, nor in the transmit shift register.
This bit is cleared by writing a one to CR.STTBRK.
0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero.
1: There has been a time-out since the last Start Time-out command.
This bit is cleared by writing a one to CR.STTTO or CR.RETTO.
0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA.
1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
0: No stop bit has been found as low since the last RSTSTA.
1: At least one stop bit has been found as low since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
0: No Break received or End of Break detected since the last RSTSTA.
1: Break received or End of Break detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an
STTBRK command has been requested. As soon as the transmitter is enabled, TXRDY is set.
1: There is no character in the THR.
This bit is cleared by writing a one to CR.STTBRK.
0: The receiver is either disabled, or no complete character has been received since the last read of RHR. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and RHR has not yet been read.
337
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