AT32UC3B1512 Atmel Corporation, AT32UC3B1512 Datasheet - Page 552
AT32UC3B1512
Manufacturer Part Number
AT32UC3B1512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1512
Flash (kbytes)
512 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1512-Z1UT
Manufacturer:
ROHM
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
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25.7.6
Name:
Access Type:
Offset:
Reset Value:
• RXBUFF: RX Buffer Full
• ENDRX: End of RX Buffer
• GOVRE: General Overrun Error
• DRDY: Data Ready
• OVREn: Overrun Error n
• EOCn: End of Conversion n
32059L–AVR32–01/2012
OVRE7
EOC7
31
23
15
–
–
7
This bit is set when the Buffer Full signal from the Peripheral DMA is active.
This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive.
This bit is set when the End Receive signal from the Peripheral DMA is active.
This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.
This bit is set when a General Overrun Error has occurred.
This bit is cleared when the SR register is read.
1: At least one General Overrun Error has occurred since the last read of the SR register.
0: No General Overrun Error occurred since the last read of the SR register.
This bit is set when a data has been converted and is available in the LCDR register.
This bit is cleared when the LCDR register is read.
0: No data has been converted since the last read of the LCDR register.
1: At least one data has been converted and is available in the LCDR register.
These bits are set when an overrun error on the corresponding channel has occurred (if implemented).
These bits are cleared when the SR register is read.
0: No overrun error on the corresponding channel (if implemented) since the last read of SR.
1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.
These bits are set when the corresponding conversion is complete.
These bits are cleared when the corresponding CDR or LCDR registers are read.
0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.
1: Corresponding analog channel (if implemented) is enabled and conversion is complete.
Status Register
OVRE6
EOC6
30
22
14
SR
Read-only
0x1C
0x000C0000
–
–
6
OVRE5
EOC5
29
21
13
–
–
5
OVRE4
EOC4
28
20
12
–
–
4
RXBUFF
OVRE3
EOC3
27
19
11
–
3
ENDRX
OVRE2
EOC2
26
18
10
–
2
GOVRE
OVRE1
EOC1
25
17
–
9
1
OVRE0
DRDY
EOC0
24
16
–
8
0
552
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